公开(公告)号：US20210013585A1

公开(公告)日：2021-01-14

申请号：US16506654

申请日：2019-07-09

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Lin Ho ,  Chih-Cheng Lee ,  Chun Chen Chen ,  Yuanhao Yu

IPC: H01Q1/22 ,  H01L23/66

Abstract: A semiconductor device package includes a substrate and an antenna module. The substrate has a first surface and a second surface opposite to the first surface. The antenna module is disposed on the first surface of the substrate with a gap. The antenna module has a support and an antenna layer. The support has a first surface facing away from the substrate and a second surface facing the substrate. The antenna layer is disposed on the first surface of the support. The antenna layer has a first antenna pattern and a first dielectric layer.

公开(公告)号：US10734704B2

公开(公告)日：2020-08-04

申请号：US16197352

申请日：2018-11-20

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Lin Ho ,  Chih-Cheng Lee

IPC: H01Q1/22 ,  H01Q23/00 ,  H01Q9/04 ,  H01Q21/06 ,  H01L23/66 ,  H01Q21/00 ,  H01L23/00

Abstract: An antenna package includes a patterned antenna structure and an encapsulant. The patterned antenna structure includes a first surface, a second surface opposite the first surface and a third surface extended between the first surface and the second surface. The encapsulant is disposed on the first surface of the patterned antenna structure. The third surface of the patterned antenna structure includes a first portion covered by the encapsulant and a second portion exposed from the encapsulant.

公开(公告)号：US10083902B2

公开(公告)日：2018-09-25

申请号：US15208569

申请日：2016-07-12

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yuan-Chang Su ,  Chih-Cheng Lee ,  Cheng-Lin Ho

IPC: H01L23/498 ,  H05K1/18 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49866 ,  H01L2924/0002 ,  H05K1/188 ,  H01L2924/00

Abstract: Disclosed is a semiconductor package structure and manufacturing method. The semiconductor package structure includes a first dielectric layer, a second dielectric layer, a component, a patterned conductive layer and at least two conductive vias. The first dielectric layer has a first surface and a second surface opposite the first surface. The second dielectric layer has a first surface and a second surface opposite the first surface. The second surface of the first dielectric layer is attached to the first surface of the second dielectric layer. A component within the second dielectric layer has at least two electrical contacts adjacent to the second surface of the first dielectric layer. The patterned conductive layer within the first dielectric layer is adjacent to the first surface of the first dielectric layer. The conductive vias penetrate the first dielectric layer and electrically connect the electrical contacts with the patterned conductive layer.

公开(公告)号：US09583427B2

公开(公告)日：2017-02-28

申请号：US15138107

申请日：2016-04-25

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih-Cheng Lee ,  Yuan Chang Su ,  Cheng-Lin Ho ,  Chung-Ming Wu ,  You-Lung Yen

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/76801 ,  H01L21/76877 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/11334 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16113 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/81801 ,  H01L2924/014 ,  H01L2924/00014

Abstract: The present disclosure relates to a semiconductor substrate, a semiconductor package structure, and methods for making the same. A method includes providing a substrate and a carrier layer. The substrate includes a first patterned metal layer, a second patterned metal layer spaced from the first patterned metal layer, and a dielectric layer disposed between the first patterned metal layer and the second patterned metal layer. The dielectric layer covers the second patterned metal layer. The dielectric layer defines first openings exposing the second patterned metal layer, and further defines a via opening extending from the first patterned metal layer to the second patterned metal layer. A conductive material is disposed in the via and electrically connects the first patterned metal layer to the second patterned metal layer. The carrier layer defines second openings exposing the second patterned metal layer.

Abstract translation: 本公开涉及半导体衬底，半导体封装结构及其制造方法。 一种方法包括提供衬底和载体层。 衬底包括第一图案化金属层，与第一图案化金属层间隔开的第二图案化金属层，以及设置在第一图案化金属层和第二图案化金属层之间的介电层。 电介质层覆盖第二图案化金属层。 电介质层限定暴露第二图案化金属层的第一开口，并且还限定从第一图案化金属层延伸到第二图案化金属层的通孔。 导电材料设置在通孔中并将第一图案化金属层电连接到第二图案化金属层。 载体层限定暴露第二图案化金属层的第二开口。

公开(公告)号：US09420695B2

公开(公告)日：2016-08-16

申请号：US14548118

申请日：2014-11-19

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yuan-Chang Su ,  Chih-Cheng Lee ,  Cheng-Lin Ho

IPC: H01L23/552 ,  H05K1/18 ,  H01L23/498 ,  H01L21/48 ,  H05K3/30 ,  H05K3/46 ,  H05K3/10 ,  H05K3/18

CPC classification number: H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49866 ,  H01L2924/0002 ,  H05K1/188 ,  H01L2924/00

Abstract: Disclosed is a semiconductor package structure and manufacturing method. The semiconductor package structure includes a first dielectric layer, a second dielectric layer, a component, a patterned conductive layer and at least two conductive vias. The first dielectric layer has a first surface and a second surface opposite the first surface. The second dielectric layer has a first surface and a second surface opposite the first surface. The second surface of the first dielectric layer is attached to the first surface of the second dielectric layer. A component within the second dielectric layer has at least two electrical contacts adjacent to the second surface of the first dielectric layer. The patterned conductive layer within the first dielectric layer is adjacent to the first surface of the first dielectric layer. The conductive vias penetrate the first dielectric layer and electrically connect the electrical contacts with the patterned conductive layer.

Abstract translation: 公开了半导体封装结构和制造方法。 半导体封装结构包括第一电介质层，第二电介质层，部件，图案化导电层和至少两个导电通孔。 第一电介质层具有与第一表面相对的第一表面和第二表面。 第二电介质层具有与第一表面相对的第一表面和第二表面。 第一电介质层的第二表面附着到第二电介质层的第一表面。 第二电介质层内的部件具有与第一电介质层的第二表面相邻的至少两个电触点。 第一介电层内的图案化导电层与第一介电层的第一表面相邻。 导电通孔穿透第一电介质层并将电触点与图案化的导电层电连接。