公开(公告)号：US20230295794A1

公开(公告)日：2023-09-21

申请号：US18201442

申请日：2023-05-24

Applicant: Applied Materials, Inc.

Inventor： Lakmal C. Kalutarage ,  Bhaskar Jyoti Bhuyan ,  Aaron Dangerfield ,  Feng Q. Liu ,  Mark Saly ,  Michael Haverty ,  Muthukumar Kaliappan

IPC: C23C16/04 ,  C23C16/02 ,  C23C16/56 ,  H01L21/32 ,  H01L21/02

CPC classification number: C23C16/042 ,  C23C16/0272 ,  C23C16/56 ,  H01L21/32 ,  H01L21/0228 ,  H01L21/02172 ,  H01L21/02211 ,  H01L21/0217

Abstract: Methods of selectively depositing blocking layers on conductive surfaces over dielectric surfaces are described. In some embodiments, a 4-8 membered substituted heterocycle is exposed to a substrate to selectively form a blocking layer. In some embodiments, a layer is selectively deposited on the dielectric surface after the blocking layer is formed. In some embodiments, the blocking layer is removed.

公开(公告)号：US20230070489A1

公开(公告)日：2023-03-09

申请号：US17845356

申请日：2022-06-21

Applicant: Applied Materials, Inc.

Inventor： Michael Haverty ,  Lu Chen ,  Muthukumar Kaliappan

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/285

Abstract: Described are microelectronic devices and methods for forming interconnections in microelectronic devices. Embodiments of microelectronic devices include tantalum-containing barrier films comprising an alloy of tantalum and a metal dopant selected from the group consisting of ruthenium (Ru), osmium (Os), palladium (Pd), platinum (Pt), and iridium (Ir).

公开(公告)号：US20220406595A1

公开(公告)日：2022-12-22

申请号：US17355154

申请日：2021-06-22

Applicant: Applied Materials, Inc. ,  National University of Singapore

Inventor： Chandan Kr Barik ,  Doreen Wei Ying Yong ,  John Sudijono ,  Cong Trinh ,  Bhaskar Jyoti Bhuyan ,  Michael Haverty ,  Muthukumar Kaliappan ,  Yingqian Chen ,  Anil Kumar Tummanapelli ,  Richard Ming Wah Wong

IPC: H01L21/02 ,  C23C16/34 ,  C23C16/40 ,  C23C16/455

Abstract: Novel cyclic silicon precursors and oxidants are described. Methods for depositing silicon-containing films on a substrate are described. The substrate is exposed to a silicon precursor and a reactant to form the silicon-containing film (e.g., elemental silicon, silicon oxide, silicon nitride). The exposures can be sequential or simultaneous.

公开(公告)号：US20220372616A1

公开(公告)日：2022-11-24

申请号：US17315223

申请日：2021-05-07

Applicant: Applied Materials, Inc.

Inventor： Lakmal C. Kalutarage ,  Bhaskar Jyoti Bhuyan ,  Aaron Dangerfield ,  Feng Q. Liu ,  Mark Saly ,  Michael Haverty ,  Muthukumar Kaliappan

IPC: C23C16/04 ,  C23C16/56 ,  C23C16/02

Abstract: Methods of selectively depositing blocking layers on conductive surfaces over dielectric surfaces are described. In some embodiments, a 4-8 membered substituted heterocycle is exposed to a substrate to selectively form a blocking layer. In some embodiments, a layer is selectively deposited on the dielectric surface after the blocking layer is formed. In some embodiments, the blocking layer is removed.

公开(公告)号：US20220230874A1

公开(公告)日：2022-07-21

申请号：US17151240

申请日：2021-01-18

Applicant: Applied Materials, Inc. ,  National University of Singapore

Inventor： Chandan Kr Barik ,  Michael Haverty ,  Muthukumar Kaliappan ,  Cong Trinh ,  Bhaskar Jyoti Bhuyan ,  John Sudijono ,  Anil Kumar Tummanapelli ,  Richard Ming Wah Wong ,  Yingqian Chen

IPC: H01L21/02 ,  C23C16/34 ,  C23C16/455 ,  C23C16/44

Abstract: Chalcogen silane precursors are described. Methods for depositing a silicon nitride (SixNy) film on a substrate are described. The substrate is exposed to the chalcogen silane and a reactant to deposit the silicon nitride (SixNy) film. The exposures can be sequential or simultaneous. The chalcogen silane may be substantially free of halogen. The chalcogen may be selected from the group consisting of sulfur (S), selenium (Se), and tellurium (Te).

公开(公告)号：US20210350219A1

公开(公告)日：2021-11-11

申请号：US17380318

申请日：2021-07-20

Applicant: Applied Materials, Inc.

Inventor： Milan Pesic ,  Shruba Gangopadhyay ,  Muthukumar Kaliappan ,  Michael Haverty

IPC: G06N3/063 ,  G11C11/54 ,  H01L27/24 ,  H01L45/00 ,  G11C13/00

Abstract: A crested barrier memory device may include a first electrode, a first self- rectifying layer, and a combined barrier and active layer. The first self-rectifying layer may be between the first electrode and the active layer. A conduction band offset between the first self-rectifying layer and the combined barrier and active layer may be greater than approximately 1.5 eV. A valence band offset between the first self-rectifying layer and the combined barrier and active layer may be less than approximately −0.5 eV. The device may also include a second electrode. The active layer may be between the first self-rectifying layer and the second electrode.