公开(公告)号：US20200266262A1

公开(公告)日：2020-08-20

申请号：US16401736

申请日：2019-05-02

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Cheng-Hung Shih ,  Nian-Cih Yang ,  Yi-Cheng Chen ,  Shang-Jan Yang

IPC: H01L49/02 ,  H01L23/64

Abstract: A semiconductor device having 3D inductor includes a first transverse inductor, a longitudinal inductor and a second transverse inductor. The first transverse inductor is formed on a first substrate, the second transverse inductor and the longitudinal inductor are formed on a second substrate. The second substrate is bonded to the first substrate to connect the first transverse inductor and the longitudinal inductor such that the first transverse inductor, the longitudinal inductor and the second transverse inductor compose a 3D inductor.

公开(公告)号：US20200091385A1

公开(公告)日：2020-03-19

申请号：US16260528

申请日：2019-01-29

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chin-Tang Hsieh ,  Cheng-Hung Shih

IPC: H01L33/62 ,  H01L33/38

Abstract: A microchip is electrically connected to a substrate to become a chip package, preferably for LED. A chip of the package includes a body and at least one electrode which is disposed and exposed on a surface of the body. The electrode includes a confining groove and a confining wall. The confining wall is peripherally located around the confining groove and provided to confine at least one conductive particle of an adhesive in the confining groove. The electrode of the chip is electrically connected to a bonding pad of a substrate via the conductive particle confined in the confining groove.

公开(公告)号：US09230823B1

公开(公告)日：2016-01-05

申请号：US14530896

申请日：2014-11-03

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Cheng-Hung Shih ,  Kuo-Hua Yang ,  Hsiang-Pin Hou

IPC: H01L21/44 ,  H01L21/311

CPC classification number: H01L21/31133 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/1181 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/014

Abstract: A method of photoresist strip includes providing a semiconductor substrate and performing an immerse step and a strip step, wherein the semiconductor substrate comprises a base, a bonding pad, a protective layer, an under bump metallurgy layer, a patterned photoresist layer and a bump. The patterned photoresist layer covers the under bump metallurgy layer and a lateral surface of the bump, wherein a first connection interface is formed between the patterned photoresist layer and the lateral surface of the bump, and a second connection interface is formed between the patterned photoresist layer and the under bump metallurgy layer. In the immerse step, the patterned photoresist layer contacts with a chemical solution which degrades the bond strength of the first connection interface. Therefore, in the strip step, the semiconductor substrate is scoured by a flow with appropriate force of impact, which strips the patterned photoresist layer from the base.

Abstract translation: 光致抗蚀剂条的方法包括提供半导体衬底并执行浸渍步骤和条带步骤，其中半导体衬底包括基底，焊盘，保护层，凸块下金属层，图案化光刻胶层和凸块。 图案化的光致抗蚀剂层覆盖下凸块冶金层和凸块的侧表面，其中在图案化的光致抗蚀剂层和凸块的侧表面之间形成第一连接界面，并且第二连接界面形成在图案化的光致抗蚀剂层 和凸块下金属层。 在浸渍步骤中，图案化的光致抗蚀剂层与降低第一连接界面的结合强度的化学溶液接触。 因此，在带状步骤中，通过具有适当的冲击力的流动来冲洗半导体衬底，从底部剥离图案化的光致抗蚀剂层。