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    Method of manufacturing embedded wiring board
    21.
    发明授权
    Method of manufacturing embedded wiring board 有权
    嵌入式布线板的制造方法

    公开(公告)号：US09210815B2

    公开(公告)日：2015-12-08

    申请号：US13474735

    申请日：2012-05-18

    Applicant: Cheng-Po Yu

    Inventor： Cheng-Po Yu

    IPC: H05K3/36 ,  H05K3/00 ,  H05K3/46 ,  H05K3/10

    CPC classification number: H05K3/0035 ,  H05K3/107 ,  H05K3/465 ,  H05K2201/0236 ,  H05K2201/0959 ,  H05K2201/09845 ,  H05K2203/1476 ,  Y10T29/49155

    Abstract: A manufacturing method of an embedded wiring board is provided. The method includes the following steps. First, an insulation layer and a lower wiring layer are provided, wherein the insulation layer includes a polymeric material. Then, the plural catalyst grains are distributed in the polymeric material. A groove and an engraved pattern are formed on the upper surface. A blind via is formed on a bottom surface of the groove to expose the lower pad. An upper wiring layer is formed in the engraved pattern. Some catalyst grains are exposed and activated in the groove, the engraved pattern and the blind via. A first conductive pillar is formed in the groove. Finally, a second conductive pillar is formed in the blind via.

    Abstract translation: 提供了一种嵌入式布线板的制造方法。 该方法包括以下步骤。 首先，提供绝缘层和下布线层，其中绝缘层包括聚合材料。 然后，多个催化剂颗粒分布在聚合物材料中。 在上表面上形成有凹槽和雕刻图案。 在槽的底表面上形成盲孔以露出下垫。 上部布线层形成在雕刻图案中。 一些催化剂颗粒在凹槽，雕刻图案和盲孔中暴露和活化。 第一导电柱形成在凹槽中。 最后，在盲通孔中形成第二导电柱。

    Circuit structure
    24.
    发明授权
    Circuit structure 有权
    电路结构

    公开(公告)号：US08288662B2

    公开(公告)日：2012-10-16

    申请号：US12718194

    申请日：2010-03-05

    Applicant: Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

    Inventor： Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

    IPC: H05K1/11

    CPC classification number: H05K3/184 ,  H05K3/0032 ,  H05K3/387 ,  H05K3/421 ,  H05K3/465 ,  H05K3/4661 ,  H05K2201/0195 ,  H05K2201/0347 ,  H05K2203/107 ,  H05K2203/1173

    Abstract: A circuit structure including a circuit board, an insulating layer, a conductive via, a platable dielectric layer and a conductive pattern is provided. The insulating layer is disposed on the circuit board and covers a circuit layer of the circuit board. The conductive via passes through the insulating layer and connects the circuit layer and protrudes from a surface of the insulating layer. The platable dielectric layer having a trench pattern is disposed on the surface of the insulating layer wherein the portion of the conductive via protruding from the surface is located in the trench pattern. The material of the platable dielectric layer includes a chemical platable material. The conductive pattern is in the trench pattern and connects the conductive via wherein an interface exists between the conductive pattern and the conductive via and protrudes from the surface of the insulating layer.

    Abstract translation: 提供了包括电路板，绝缘层，导电通孔，可镀介电层和导电图案的电路结构。 绝缘层设置在电路板上并覆盖电路板的电路层。 导电通孔穿过绝缘层并连接电路层并从绝缘层的表面突出。 具有沟槽图案的可镀介电层设置在绝缘层的表面上，其中从表面突出的导电通孔的部分位于沟槽图案中。 可镀介电层的材料包括化学镀层材料。 导电图案处于沟槽图案中并且连接导电通孔，其中在导电图案和导电通孔之间存在界面，并从绝缘层的表面突出。

    Circuit substrate and manufacturing method thereof
    25.
    发明授权
    Circuit substrate and manufacturing method thereof 有权
    电路基板及其制造方法

    公开(公告)号：US08247705B2

    公开(公告)日：2012-08-21

    申请号：US12718226

    申请日：2010-03-05

    Applicant: Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

    Inventor： Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

    IPC: H05K1/11

    CPC classification number: H05K3/387 ,  C23C18/1653 ,  H05K3/4644 ,  H05K2201/0129 ,  H05K2201/0145 ,  H05K2201/0154 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T428/24322

    Abstract: A manufacturing method of a circuit substrate includes the following steps. A dielectric layer is formed on at least one surface of a substrate. An insulating layer is formed on the dielectric layer. A portion of the insulating layer and a portion of the dielectric layer are removed, so as to form at least one blind via in the dielectric layer and the insulating layer. An electroless plating layer is formed on the sidewall of the blind via and a remaining portion of the insulating layer, wherein the binding strength between the insulating layer and the electroless plating layer is greater than that between the dielectric layer and the electroless plating layer. A patterned conductive layer is plated to cover the electroless plating layer.

    Abstract translation: 电路基板的制造方法包括以下步骤。 在基板的至少一个表面上形成介电层。 在电介质层上形成绝缘层。 去除绝缘层的一部分和电介质层的一部分，以在电介质层和绝缘层中形成至少一个盲孔。 在盲通孔的侧壁和绝缘层的剩余部分上形成化学镀层，其中绝缘层和化学镀层之间的结合强度大于介电层和化学镀层之间的结合强度。 电镀图案化导电层以覆盖化学镀层。

    CIRCUIT SUBSTRATE AND MANUFACTURING METHOD THEREOF
    26.
    发明申请
    CIRCUIT SUBSTRATE AND MANUFACTURING METHOD THEREOF 有权
    电路基板及其制造方法

    公开(公告)号：US20110155427A1

    公开(公告)日：2011-06-30

    申请号：US12718226

    申请日：2010-03-05

    Applicant: Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

    Inventor： Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

    IPC: H05K1/09 ,  B05D5/12 ,  H05K1/11 ,  H05K1/02

    CPC classification number: H05K3/387 ,  C23C18/1653 ,  H05K3/4644 ,  H05K2201/0129 ,  H05K2201/0145 ,  H05K2201/0154 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T428/24322

    Abstract: A manufacturing method of a circuit substrate includes the following steps. A dielectric layer is formed on at least one surface of a substrate. An insulating layer is formed on the dielectric layer. A portion of the insulating layer and a portion of the dielectric layer are removed, so as to form at least one blind via in the dielectric layer and the insulating layer. An electroless plating layer is formed on the sidewall of the blind via and a remaining portion of the insulating layer, wherein the binding strength between the insulating layer and the electroless plating layer is greater than that between the dielectric layer and the electroless plating layer. A patterned conductive layer is plated to cover the electroless plating layer.

    Abstract translation: 电路基板的制造方法包括以下步骤。 在基板的至少一个表面上形成介电层。 在电介质层上形成绝缘层。 去除绝缘层的一部分和电介质层的一部分，以在电介质层和绝缘层中形成至少一个盲孔。 在盲通孔的侧壁和绝缘层的剩余部分上形成化学镀层，其中绝缘层和化学镀层之间的结合强度大于介电层和化学镀层之间的结合强度。 电镀图案化导电层以覆盖化学镀层。

    CIRCUIT STRUCTURE
    27.
    发明申请
    CIRCUIT STRUCTURE 有权
    电路结构

    公开(公告)号：US20110094779A1

    公开(公告)日：2011-04-28

    申请号：US12718194

    申请日：2010-03-05

    Applicant: Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

    Inventor： Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

    IPC: H05K1/02 ,  H05K1/11

    CPC classification number: H05K3/184 ,  H05K3/0032 ,  H05K3/387 ,  H05K3/421 ,  H05K3/465 ,  H05K3/4661 ,  H05K2201/0195 ,  H05K2201/0347 ,  H05K2203/107 ,  H05K2203/1173

    Abstract: A circuit structure including a circuit board, an insulating layer, a conductive via, a platable dielectric layer and a conductive pattern is provided. The insulating layer is disposed on the circuit board and covers a circuit layer of the circuit board. The conductive via passes through the insulating layer and connects the circuit layer and protrudes from a surface of the insulating layer. The platable dielectric layer having a trench pattern is disposed on the surface of the insulating layer wherein the portion of the conductive via protruding from the surface is located in the trench pattern. The material of the platable dielectric layer includes a chemical platable material. The conductive pattern is in the trench pattern and connects the conductive via wherein an interface exists between the conductive pattern and the conductive via and protrudes from the surface of the insulating layer.

    Abstract translation: 提供了包括电路板，绝缘层，导电通孔，可镀介电层和导电图案的电路结构。 绝缘层设置在电路板上并覆盖电路板的电路层。 导电通孔穿过绝缘层并连接电路层并从绝缘层的表面突出。 具有沟槽图案的可镀介电层设置在绝缘层的表面上，其中从表面突出的导电通孔的部分位于沟槽图案中。 可镀介电层的材料包括化学镀层材料。 导电图案处于沟槽图案中并且连接导电通孔，其中在导电图案和导电通孔之间存在界面，并从绝缘层的表面突出。

    METHOD OF FABRICATING SUBSTRATE
    30.
    发明申请
    METHOD OF FABRICATING SUBSTRATE 有权
    制造基板的方法

    公开(公告)号：US20090197364A1

    公开(公告)日：2009-08-06

    申请号：US12422428

    申请日：2009-04-13

    Applicant: Tzyy-Jang Tseng ,  Chih-Ming Chang ,  Cheng-Po Yu ,  Chung W. Ho

    Inventor： Tzyy-Jang Tseng ,  Chih-Ming Chang ,  Cheng-Po Yu ,  Chung W. Ho

    IPC: H01L21/02 ,  H01L21/78

    CPC classification number: H01L23/142 ,  H01L21/6835 ,  H01L33/486 ,  H01L33/62 ,  H01L33/642 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/181 ,  H05K3/06 ,  H05K3/202 ,  H05K2201/09881 ,  H05K2203/0369 ,  H05K2203/1476 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

    Abstract: A method of fabricating a substrate includes following steps. First, a metallic panel having a first surface and a second surface is provided. A first half-etching process is carried out to etch the first surface of the metallic panel to a first depth so that a first patterned metallic layer is formed on the first surface. Next, a first insulating material is deposited into gaps in the first patterned metallic layer to form a first insulator. Thereafter, a second half-etching process is carried out to etch the second surface of the metallic panel to a second depth and expose at least a portion of the first insulator so that a second patterned metallic layer is formed on the second surface. The first depth and the second depth together equal the thickness of the metallic panel.

    Abstract translation: 制造衬底的方法包括以下步骤。 首先，提供具有第一表面和第二表面的金属板。 执行第一半蚀刻工艺以将金属板的第一表面蚀刻到第一深度，使得在第一表面上形成第一图案化金属层。 接下来，将第一绝缘材料沉积在第一图案化金属层中的间隙中以形成第一绝缘体。 此后，执行第二半蚀刻工艺以将金属板的第二表面蚀刻到第二深度，并且暴露第一绝缘体的至少一部分，使得在第二表面上形成第二图案化金属层。 第一深度和第二深度一起等于金属面板的厚度。

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