公开(公告)号：US20180027659A1

公开(公告)日：2018-01-25

申请号：US15494672

申请日：2017-04-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Andreas Huber ,  Harald Huels ,  Stefano S. Oggioni ,  Thomas Strach ,  Thomas-Michael Winkel

IPC: H05K1/18 ,  H05K3/46 ,  H05K1/02 ,  H05K3/00 ,  H05K1/11 ,  H05K3/34 ,  H05K1/14 ,  H05K3/18

CPC classification number: H05K1/183 ,  H01L23/49838 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06537 ,  H01L2225/06548 ,  H05K1/0219 ,  H05K1/115 ,  H05K1/144 ,  H05K1/181 ,  H05K3/0097 ,  H05K3/18 ,  H05K3/34 ,  H05K3/4697 ,  H05K2201/049 ,  H05K2201/10015 ,  H05K2201/10106

Abstract: The invention relates to a method for embedding a discrete electronic device in a chip module. The chip module comprises a multilayer substrate which comprises a plurality of electrically conductive layers stacked above each other and an electrically non-conductive layer arranged between each pair of electrically conductive layers. The chip module is configured to receive one or more chips to be mounted onto a top surface thereof. Each electrically conductive layer comprises one or more electrically conductive structures. A recess is provided in a side surface of the chip module. The discrete electronic device is inserted into the recess. A first electrically conductive connection between a first electrical contact of the discrete electronic device and a first electrically conductive structure is established. Further, a second electrically conductive connection between a second electrical contact of the discrete electronic device and a second electrically conductive structure is established.

公开(公告)号：US09839131B2

公开(公告)日：2017-12-05

申请号：US14918678

申请日：2015-10-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce J. Chamberlin ,  Andreas Huber ,  Harald Huels ,  Thomas Strach ,  Thomas-Michael Winkel

IPC: H05K1/18 ,  H05K1/11 ,  H05K3/00 ,  H05K3/46 ,  H05K1/02 ,  H05K3/40 ,  H05K1/09 ,  H05K1/16

CPC classification number: H05K1/184 ,  B23K1/0016 ,  H05K1/0298 ,  H05K1/092 ,  H05K1/111 ,  H05K1/113 ,  H05K1/116 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K1/185 ,  H05K1/186 ,  H05K3/0047 ,  H05K3/3447 ,  H05K3/429 ,  H05K3/46 ,  H05K3/4644 ,  H05K3/4697 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09327 ,  H05K2201/09345 ,  H05K2201/09381 ,  H05K2201/09518 ,  H05K2201/09545 ,  H05K2201/096 ,  H05K2201/09845 ,  H05K2201/10 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/1003 ,  H05K2201/1006 ,  H05K2201/10174

Abstract: Embedding a discrete electrical device in a printed circuit board (PCB) includes: providing a vertical via as a blind hole from a horizontal surface of the PCB to an electrically conductive structure in a first layer, the first layer being one layer of a first core section of a plurality of core sections vertically arranged above each other, each core section including lower and upper conductive layers, and a non-conductive layer in between; inserting the electrical device into the via, with the device extending within at least two of the core sections; establishing a first electrical connection between a first electrical device contact device and the electrically conductive structure in the first layer; and establishing a second electrical connection between a second electrical device contact and a second layer, the second layer being one of the electrically conductive layers of a second horizontal core section.

公开(公告)号：US09740813B1

公开(公告)日：2017-08-22

申请号：US15292422

申请日：2016-10-13

Applicant: International Business Machines Corporation

Inventor： Martin Eckert ,  Thomas Gentner ,  Jens Kuenzer ,  Antje Mueller ,  Thomas Strach ,  Otto A. Torreiter

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5009 ,  G06F17/5036 ,  G06F17/5081 ,  G06F2217/84

Abstract: An aspect includes forming a layout effect characterization circuit by incorporating a plurality of inverting device chains including a reference chain and one or more chains having a different inverting device arrangement and a same number of inverting devices per chain in an integrated circuit layout. A low pass filter is coupled to an output of the inverting device chains to produce a filtered output. An output capture circuit is coupled to the filtered output to enable a comparison of a captured filtered output of the one or more chains having the different inverting device arrangement to a captured filtered output of the reference chain.

公开(公告)号：US09679099B2

公开(公告)日：2017-06-13

申请号：US14788819

申请日：2015-07-01

Applicant: International Business Machines Corporation

Inventor： Harry Barowski ,  Joachim Keinert ,  Sourav Saha ,  Thomas Strach

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/82 ,  G06F2217/84

Abstract: A method, executed by one or more processors, includes receiving IR-drop information as a function of location for a placement for a plurality of circuit blocks corresponding to an integrated circuit, calculating a target density for decoupling capacitors as a function of location based on the IR-drop information, placing a plurality of decoupling capacitors according to the target density to provide placed decoupling capacitors. The placed decoupling capacitors may be locally clustered to improve decoupling performance. The method may also include incrementally moving circuit elements or placed decoupling capacitors to avoid collisions within one or more circuit blocks, and routing the integrated circuit. A corresponding computer program product and computer system are also disclosed herein.

公开(公告)号：US09673179B1

公开(公告)日：2017-06-06

申请号：US15214565

申请日：2016-07-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Andreas Huber ,  Harald Huels ,  Stefano S. Oggioni ,  Thomas Strach ,  Thomas-Michael Winkel

IPC: H01L25/065 ,  H01L23/498

CPC classification number: H05K1/183 ,  H01L23/49838 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06537 ,  H01L2225/06548 ,  H05K1/0219 ,  H05K1/115 ,  H05K1/144 ,  H05K1/181 ,  H05K3/0097 ,  H05K3/18 ,  H05K3/34 ,  H05K3/4697 ,  H05K2201/049 ,  H05K2201/10015 ,  H05K2201/10106

Abstract: The invention relates to a method for embedding a discrete electronic device in a chip module. The chip module comprises a multilayer substrate which comprises a plurality of electrically conductive layers stacked above each other and an electrically non-conductive layer arranged between each pair of electrically conductive layers. The chip module is configured to receive one or more chips to be mounted onto a top surface thereof. Each electrically conductive layer comprises one or more electrically conductive structures. A recess is provided in a side surface of the chip module. The discrete electronic device is inserted into the recess. A first electrically conductive connection between a first electrical contact of the discrete electronic device and a first electrically conductive structure is established. Further, a second electrically conductive connection between a second electrical contact of the discrete electronic device and a second electrically conductive structure is established.

公开(公告)号：US20170004248A1

公开(公告)日：2017-01-05

申请号：US14925097

申请日：2015-10-28

Applicant: International Business Machines Corporation

Inventor： Harry Barowski ,  Joachim Keinert ,  Sourav Saha ,  Thomas Strach

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/82 ,  G06F2217/84

Abstract: A method, executed by one or more processors, includes receiving IR-drop information as a function of location for a placement for a plurality of circuit blocks corresponding to an integrated circuit, calculating a target density for decoupling capacitors as a function of location based on the IR-drop information, placing a plurality of decoupling capacitors according to the target density to provide placed decoupling capacitors. The placed decoupling capacitors may be locally clustered to improve decoupling performance. The method may also include incrementally moving circuit elements or placed decoupling capacitors to avoid collisions within one or more circuit blocks, and routing the integrated circuit. A corresponding computer program product and computer system are also disclosed herein.

公开(公告)号：US09141421B2

公开(公告)日：2015-09-22

申请号：US13693386

申请日：2012-12-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Lee E. Eisen ,  Michael S. Floyd ,  Thomas Strach ,  Huajun Wen ,  Tingdong Zhou

IPC: G06F1/26 ,  G06F1/32 ,  G06F9/46 ,  G06F11/30

CPC classification number: G06F9/46 ,  G06F1/26 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3243 ,  G06F1/329 ,  G06F11/3024 ,  G06F2201/86 ,  Y02D10/24

Abstract: In the management of a processor, logical operation activity is monitored for increases from a low level to a high level during a sampling window across multiple cores sharing a common supply rail, with at least one decoupling capacitor along the common supply rail. Responsive to detecting the increase in logical operation activity from the low level to the high level during the sampling window, the processor limits the logical operations executed on the cores during a lower activity period to a level of logical operations set between the low level and a medium level, where the medium level is an amount between the low level and the high level. Responsive to the lower activity period ending, the processor gradually decreases the limit on the logical operations to resume normal operations.

Abstract translation: 在处理器的管理中，监视逻辑运行活动，以在共享共同供电轨的多个核心的采样窗口期间从低电平增加到高电平，沿着公共电源轨具有至少一个去耦电容器。 响应于在采样窗口期间检测从低电平到高电平的逻辑运算活动的增加，处理器将在较低活动期间内的核上执行的逻辑运算限制在低电平和低电平之间设置的逻辑运算电平 中等水平，中等水平是低水平和高水平之间的量。 响应于较低活动期结束，处理器逐渐减少逻辑运行的限制，以恢复正常运行。

公开(公告)号：US20140157277A1

公开(公告)日：2014-06-05

申请号：US14057984

申请日：2013-10-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Lee E. Eisen ,  Michael S. Floyd ,  Thomas Strach ,  Huajun Wen ,  Tingdong Zhou

IPC: G06F9/46

CPC classification number: G06F9/46 ,  G06F1/26 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3243 ,  G06F1/329 ,  G06F11/3024 ,  G06F2201/86 ,  Y02D10/24

Abstract: In the management of a processor, logical operation activity is monitored for increases from a low level to a high level during a sampling window across multiple cores sharing a common supply rail, with at least one decoupling capacitor along the common supply rail. Responsive to detecting the increase in logical operation activity from the low level to the high level during the sampling window, the processor limits the logical operations executed on the cores during a lower activity period to a level of logical operations set between the low level and a medium level, where the medium level is an amount between the low level and the high level. Responsive to the lower activity period ending, the processor gradually decreases the limit on the logical operations to resume normal operations.

公开(公告)号：US20140157033A1

公开(公告)日：2014-06-05

申请号：US13693386

申请日：2012-12-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Lee E. Eisen ,  Michael S. Floyd ,  Thomas Strach ,  Huajun Wen ,  Tingdong Zhou

IPC: G06F1/32

CPC classification number: G06F9/46 ,  G06F1/26 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3243 ,  G06F1/329 ,  G06F11/3024 ,  G06F2201/86 ,  Y02D10/24

Abstract: In the management of a processor, logical operation activity is monitored for increases from a low level to a high level during a sampling window across multiple cores sharing a common supply rail, with at least one decoupling capacitor along the common supply rail. Responsive to detecting the increase in logical operation activity from the low level to the high level during the sampling window, the processor limits the logical operations executed on the cores during a lower activity period to a level of logical operations set between the low level and a medium level, where the medium level is an amount between the low level and the high level. Responsive to the lower activity period ending, the processor gradually decreases the limit on the logical operations to resume normal operations.

Abstract translation: 在处理器的管理中，监视逻辑运行活动，以在共享共同供电轨的多个核心的采样窗口期间从低电平增加到高电平，沿着公共电源轨具有至少一个去耦电容器。 响应于在采样窗口期间检测从低电平到高电平的逻辑运算活动的增加，处理器将在较低活动期间内的核上执行的逻辑运算限制在低电平和低电平之间设置的逻辑运算电平 中等水平，中等水平是低水平和高水平之间的量。 响应于较低活动期结束，处理器逐渐减少逻辑运行的限制，以恢复正常运行。