公开(公告)号：US20180343745A1

公开(公告)日：2018-11-29

申请号：US15605353

申请日：2017-05-25

Applicant: TT Electronics PLC

Inventor： Brent Hans Larson ,  Shivesh Langhanoja

IPC: H05K1/18 ,  H05K1/11 ,  H05K1/09 ,  H05K3/32 ,  H05K3/28 ,  G01L19/00

CPC classification number: H05K1/185 ,  G01L19/0007 ,  G01L19/0076 ,  H05K1/09 ,  H05K1/111 ,  H05K1/115 ,  H05K1/16 ,  H05K1/18 ,  H05K1/181 ,  H05K3/28 ,  H05K3/32 ,  H05K7/02 ,  H05K2201/10 ,  H05K2201/10151

Abstract: A sensor device includes a printed circuit board (PCB) substrate having a top surface, a bottom surface, a slot between the top and bottom surfaces, and two holes through the top surface and reaching into the slot. The sensor device further includes a sensor chip mounted on the top surface of the PCB substrate and above one of the two holes. The sensor device further includes a molding compound covering the sensor chip and sidewall surfaces and the top surface of the PCB substrate.

公开(公告)号：US20180261578A1

公开(公告)日：2018-09-13

申请号：US15975758

申请日：2018-05-09

Applicant: PHOENIX PIONEER TECHNOLOGY CO., LTD.

Inventor： Shih-Ping HSU ,  Chao-Tsung TSENG

IPC: H01L25/065 ,  H05K1/18 ,  H01L21/683 ,  H05K3/46 ,  H01L25/00 ,  H01L23/00 ,  H01L25/16 ,  H01L23/538 ,  H05K3/00 ,  H05K1/16 ,  H05K1/02 ,  H01L23/50 ,  H01L23/498 ,  H01L21/48 ,  H05K3/28 ,  H05K3/34

CPC classification number: H01L25/0657 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/16 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16112 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2924/15153 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/0231 ,  H05K1/162 ,  H05K1/183 ,  H05K1/185 ,  H05K3/0032 ,  H05K3/0044 ,  H05K3/284 ,  H05K3/3431 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2201/10 ,  H05K2201/10007 ,  H05K2201/10015 ,  H05K2201/1003 ,  H05K2201/10037 ,  H05K2201/10545 ,  Y10T29/49131 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A method of manufacturing a package structure is provided, including forming a first wiring layer on a carrier board, forming a plurality of first conductors on the first wiring layer, forming a first insulating layer that encapsulates the first wiring layer and the first conductors, forming a second wiring layer on the first insulating layer, forming a plurality of second conductors on the second wiring layer, forming a second insulating layer that encapsulates the second wiring layer and the second conductors, and forming at least an opening on the second insulating layer for at least one electronic component to be disposed therein. Since the first and second insulating layers are formed before the opening, there is no need of stacking or laminating a substrate that already has an opening, and the electronic component will not be laminated and make a displacement. Therefore, the package structure thus manufactured has a high yield rate. The present invention further provides the package structure.

公开(公告)号：US09756732B2

公开(公告)日：2017-09-05

申请号：US14760982

申请日：2013-01-18

Applicant: MEIKO ELECTRONICS CO., LTD.

Inventor： Yasuaki Seki ,  Tomoyuki Nagata ,  Mitsuaki Toda

IPC: H05K1/18 ,  H05K1/11 ,  H05K1/02 ,  H05K3/00 ,  H01L23/00 ,  H01L23/522 ,  H05K3/30 ,  H05K3/46

CPC classification number: H05K1/186 ,  H01L23/5226 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/19 ,  H01L2224/2518 ,  H01L2224/32245 ,  H01L2224/82005 ,  H01L2224/82039 ,  H01L2224/83005 ,  H01L2224/92144 ,  H05K1/0206 ,  H05K1/0222 ,  H05K1/0298 ,  H05K1/113 ,  H05K1/114 ,  H05K1/115 ,  H05K1/185 ,  H05K1/188 ,  H05K3/0017 ,  H05K3/0035 ,  H05K3/305 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/09827 ,  H05K2201/10 ,  H05K2203/063 ,  H05K2203/1461 ,  Y10T156/10

Abstract: A device embedded substrate (20), includes: an insulation layer (12) including an insulation resin material; an electric or electronic device (4) embedded in the insulation layer (12); a terminal (15) serving as an electrode included in the device (4); a conductor pattern (18) formed on the surface of the insulation layer (12); and a conducting via (21) for electrically connecting the conductor pattern (18) and the terminals (15) with each other. The conducting via (21) is made up of a large-diameter section (21a) having a large diameter and a small-diameter section (21b) having a smaller diameter than that of the large-diameter section (21a), in order starting from the conductor pattern (18) toward the terminal (15). A stepped section (17) is formed between the large-diameter section (21a) and the small-diameter section (21b). The large-diameter section (21a) is formed so as to penetrate a sheet-shaped glass cloth (11) disposed in the insulation layer (12).

公开(公告)号：US09699909B2

公开(公告)日：2017-07-04

申请号：US14455012

申请日：2014-08-08

Applicant: IBIDEN CO., LTD.

Inventor： Naohito Ishiguro ,  Yasushi Inagaki

IPC: H05K1/18 ,  H05K7/00 ,  H05K3/46

CPC classification number: H05K1/185 ,  H01L2224/16227 ,  H01L2924/15311 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/10 ,  H05K2201/10015 ,  H05K2201/10507 ,  H05K2203/0156

Abstract: A wiring board with a built-in electronic component includes a core substrate, an electronic component in the substrate, a first upper-layer structure on first surface of the substrate, a second upper-layer structure on second surface of the substrate, and via conductors in the substrate and first upper-layer structure such that the via conductors are connected to an electrode of the component. The substrate has an accommodating layer, a first connection layer on first surface of the accommodating layer, and a second connection layer on second surface of the accommodating layer, the accommodating layer includes inner wiring and insulation layers and has cavity accommodating the component, the first connection layer includes inner wiring and insulation layers, and the second connection layer includes inner wiring and insulation layers such that the second connection layer includes greater number of inner wiring and insulation layers than the first connection layer.

公开(公告)号：US20150359096A1

公开(公告)日：2015-12-10

申请号：US14558955

申请日：2014-12-03

Applicant: PHOENIX PIONEER TECHNOLOGY CO., LTD.

Inventor： Shih-Ping HSU ,  Chao-Chung TSENG

IPC: H05K1/11 ,  H05K3/00 ,  H05K3/34 ,  H05K1/02 ,  H05K3/40 ,  H01L25/065 ,  H01L21/48 ,  H01L23/00 ,  H01L21/683 ,  H01L25/16 ,  H01L25/00 ,  H05K1/18 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/16 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/16112 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2924/15153 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/0231 ,  H05K1/162 ,  H05K1/183 ,  H05K1/185 ,  H05K3/0032 ,  H05K3/0044 ,  H05K3/284 ,  H05K3/3431 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2201/10 ,  H05K2201/10007 ,  H05K2201/10015 ,  H05K2201/1003 ,  H05K2201/10037 ,  H05K2201/10545 ,  Y10T29/49131 ,  H01L2924/014

Abstract: A method of manufacturing a package structure is provided, including forming a first wiring layer on a carrier board, forming up plurality of first conductors on the first wiring layer, forming a first insulating layer that encapsulates the first wiring layer and the first conductors, forming a second wiring layer on the first insulating layer, forming a plurality of second conductors on the second wiring layer, forming a second insulating layer that encapsulates the second wiring layer and the second conductors, and forming at least an opening on the second insulating layer for at least one electronic component to be disposed therein. Since the first and second insulating layers are formed before the opening, there is no need of stacking or laminating a substrate that already has an opening, and the electronic component will not be laminated and make a displacement. Therefore, the package structure thus manufactured has a high yield rate. The present invention further provides the package structure.

Abstract translation: 提供了一种制造封装结构的方法，包括在载体板上形成第一布线层，在第一布线层上形成多个第一导体，形成封装第一布线层和第一导体的第一绝缘层，形成 在所述第一绝缘层上形成第二布线层，在所述第二布线层上形成多个第二导体，形成封装所述第二布线层和所述第二导体的第二绝缘层，以及在所述第二绝缘层上至少形成开口 要布置在其中的至少一个电子部件。 由于在开口之前形成第一绝缘层和第二绝缘层，因此不需要堆叠或层压已经具有开口的基板，并且电子部件将不被层压并且进行位移。 因此，如此制造的封装结构具有高产率。 本发明还提供了包装结构。

公开(公告)号：US20150043183A1

公开(公告)日：2015-02-12

申请号：US14455012

申请日：2014-08-08

Applicant: IBIDEN CO., LTD.

Inventor： Naohito ISHIGURO ,  Yasushi Inagaki

IPC: H05K1/18 ,  H05K1/11 ,  H05K1/02

CPC classification number: H05K1/185 ,  H01L2224/16227 ,  H01L2924/15311 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/10 ,  H05K2201/10015 ,  H05K2201/10507 ,  H05K2203/0156

Abstract: A wiring board with a built-in electronic component includes a core substrate, an electronic component in the substrate, a first upper-layer structure on first surface of the substrate, a second upper-layer structure on second surface of the substrate, and via conductors in the substrate and first upper-layer structure such that the via conductors are connected to an electrode of the component. The substrate has an accommodating layer, a first connection layer on first surface of the accommodating layer, and a second connection layer on second surface of the accommodating layer, the accommodating layer includes inner wiring and insulation layers and has cavity accommodating the component, the first connection layer includes inner wiring and insulation layers, and the second connection layer includes inner wiring and insulation layers such that the second connection layer includes greater number of inner wiring and insulation layers than the first connection layer.

Abstract translation: 具有内置电子部件的布线基板包括芯基板，基板中的电子部件，基板第一面上的第一上层结构，基板的第二面上的第二上层结构以及基板的第二表面的通路 衬底中的导体和第一上层结构，使得通孔导体连接到部件的电极。 所述基板具有容纳层，在所述容纳层的第一表面上的第一连接层和在所述容纳层的第二表面上的第二连接层，所述容纳层包括内部布线和绝缘层，并且具有容纳所述部件的空腔，所述第一 连接层包括内部布线和绝缘层，并且第二连接层包括内部布线和绝缘层，使得第二连接层包括比第一连接层更多数量的内部布线和绝缘层。

公开(公告)号：US20100129687A1

公开(公告)日：2010-05-27

申请号：US12591549

申请日：2009-11-23

Applicant: Bongyoung Kim

Inventor： Bongyoung Kim

IPC: H01M14/00 ,  H05K1/00 ,  H05K1/09

CPC classification number: H05K3/244 ,  H01M2/26 ,  H01M10/425 ,  H05K1/00 ,  H05K3/0023 ,  H05K3/064 ,  H05K3/28 ,  H05K3/328 ,  H05K2201/10 ,  H05K2201/10037 ,  H05K2203/1115

Abstract: A secondary battery and to a circuit board for the secondary battery. The circuit board having a structure for enhancing the safety of a secondary battery, and a secondary battery with the same. The circuit board for a secondary battery includes an insulation layer, a terminal pad layer formed on the insulation layer, and a plating layer formed on the terminal pad layer. The thickness of the plating layer is greater than 20 micrometers. The plating layer is made of nickel. The secondary battery further includes a circuit protection device, and a bare cell electrically connected to the circuit protection device, wherein circuit protection device including a first lead plate electrically connected to the plating layer of the circuit board, the plating layer of the circuit board being made of the same material as that of the first lead plate of the circuit protection device.

Abstract translation: 二次电池和用于二次电池的电路板。 具有用于增强二次电池的安全性的结构的电路板和具有该二次电池的二次电池。 用于二次电池的电路板包括绝缘层，形成在绝缘层上的端子焊盘层和形成在端子焊盘层上的镀层。 镀层的厚度大于20微米。 镀层由镍制成。 二次电池还包括电路保护装置和电连接到电路保护装置的裸电池，其中电路保护装置包括电连接到电路板的镀层的第一引线板，电路板的镀层为 由与电路保护装置的第一引线板相同的材料制成。

公开(公告)号：US20180307890A1

公开(公告)日：2018-10-25

申请号：US15922348

申请日：2018-03-15

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Min Keun KIM ,  Young Sik HUR ,  Yong Ho BAEK ,  Tae Hee HAN

IPC: G06K9/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: G06K9/00053 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L2224/73204 ,  H05K1/185 ,  H05K2201/10 ,  H05K2201/10151

Abstract: A fan-out fingerprint sensor package includes a first connection member having a through-hole, a fingerprint sensor disposed in the through-hole, an encapsulant encapsulating at least portions of the first connection member and the fingerprint sensor, and a second connection member disposed on the first connection member and an active surface of the fingerprint sensor. The first connection member includes a distribution layer. The second connection member includes a first insulating layer disposed on the distribution layer and the active surface, a redistribution layer disposed on the first insulating layer, a first via connecting the redistribution layer to a connection pad of the fingerprint sensor, and a second via connecting the redistribution layer to the distribution layer. The first via passes through the first insulating layer and at least a portion of the encapsulant, and the second via passes through the first insulating layer.

公开(公告)号：US09955591B2

公开(公告)日：2018-04-24

申请号：US14802139

申请日：2015-07-17

Applicant: IBIDEN CO., LTD.

Inventor： Mitsuhiro Tomikawa ,  Koji Asano

IPC: H05K1/18 ,  H05K3/46 ,  H05K7/00 ,  H05K1/16 ,  H05K1/02 ,  H05K3/34

CPC classification number: H05K3/4697 ,  H01L21/568 ,  H01L2224/04105 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K1/0206 ,  H05K1/162 ,  H05K1/185 ,  H05K3/3436 ,  H05K3/4644 ,  H05K2201/10 ,  H05K2201/10045 ,  H05K2201/10416 ,  H01L2924/00014

Abstract: A circuit substrate includes a core substrate having a cavity penetrating through the substrate, a combined component accommodated in the cavity of the substrate, a first build-up layer laminated on first surface of the substrate and including an insulating layer such that the insulating layer is covering the cavity, a second build-up layer laminated on second surface of the substrate and including an insulating layer such that the insulating layer is covering the cavity, and a filling resin filling gap formed between the cavity and combined component accommodated in the cavity of the substrate. The combined component includes an electronic component and a metal block, the electronic component has terminal surface on side facing the first surface of the substrate, and the metal block is superposed to surface of the electronic component on the opposite side of the electronic component with respect to the terminal surface.

公开(公告)号：US09871899B2

公开(公告)日：2018-01-16

申请号：US13919033

申请日：2013-06-17

Applicant: Hyeong-Gwon Kim

Inventor： Hyeong-Gwon Kim

IPC: H05K1/00 ,  H04M1/02 ,  G09F9/30 ,  H05K1/18 ,  H05K7/00 ,  H05K1/11 ,  H05K1/14 ,  H05K3/46

CPC classification number: H04M1/0268 ,  G09F9/301 ,  H04M1/0277 ,  H05K1/118 ,  H05K1/147 ,  H05K1/185 ,  H05K3/4691 ,  H05K2201/05 ,  H05K2201/10 ,  H05K2201/10681

Abstract: A display device includes a flexible display panel for displaying an image, and a printed circuit board electrically connected with the flexible display panel through a circuit film. The printed circuit board may include a plurality of boards in a stack, the boards being respectively provided with integrated circuits, driving chips, and circuit wires, and a conducting portion connecting circuit wires of at least two boards among the plurality of boards.