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公开(公告)号：US20130322425A1
公开(公告)日：2013-12-05
申请号：US13889961
申请日：2013-05-08
Applicant: IMAGINATION TECHNOLOGIES LIMITED
Inventor： Paul Murrin , Mohammed El-Hajjar
IPC: G01R29/02
CPC classification number: G01R29/02 , H04B17/345 , H04L1/20 , H04L1/206 , H04L27/2647
Abstract: Noise variance estimation and interference detection is described. In one example, a method of estimating noise variance is described in which the pilots within a received OFDM signal are divided into bands and then a noise variance estimate is calculated on a per-band basis by averaging the noise estimates for those pilots within the band. In some examples, the pilots are divided into bands in frequency and in other examples, the pilots are divided into bands in frequency and time, such that noise estimates from more than one OFDM symbol are used in calculating the per-band noise variance estimates. The noise variance estimate for a pilot is then set to the noise variance estimate for the band which contains the pilot. The noise variance estimate for a data sub-carrier can then be determined by interpolating between the values for the pilots.
Abstract translation: 描述噪声方差估计和干扰检测。 在一个示例中，描述了估计噪声方差的方法，其中接收的OFDM信号内的导频被划分成频带，然后通过对频带内的那些导频的噪声估计进行平均来计算每个频带的噪声方差估计 。 在一些示例中，导频在频率上被划分为频带，在其他示例中，导频在频率和时间上被划分成频带，使得来自多于一个OFDM符号的噪声估计被用于计算每频带噪声方差估计。 然后将导频的噪声方差估计设置为包含导频的频带的噪声方差估计。 然后可以通过在导频的值之间进行插值来确定数据子载波的噪声方差估计。
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公开(公告)号：US11210217B2
公开(公告)日：2021-12-28
申请号：US16845303
申请日：2020-04-10
Applicant: Imagination Technologies Limited
Inventor： Paul Murrin , Adrian J. Anderson , Mohammed El-Hajjar
Abstract: Tile based interleaving and de-interleaving of row-column interleaved data is described. In one example, the de-interleaving is divided into two memory transfer stages, the first from an on-chip memory to a DRAM and the second from the DRAM to an on-chip memory. Each stage operates on part of a row-column interleaved block of data and re-orders the data items, such that the output of the second stage comprises de-interleaved data. In the first stage, data items are read from the on-chip memory according to a non-linear sequence of memory read addresses and written to the DRAM. In the second stage, data items are read from the DRAM according to bursts of linear address sequences which make efficient use of the DRAM interface and written back to on-chip memory according to a non-linear sequence of memory write addresses.
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公开(公告)号：US20210050942A1
公开(公告)日：2021-02-18
申请号：US17086576
申请日：2020-11-02
Applicant: Imagination Technologies Limited
Inventor： Filipe Carvalho , Paul Murrin
Abstract: Channel state information (CSI) scaling modules for use in a demodulator configured to demodulate a signal received over a transmission channel, the demodulator comprising a soft decision error corrector (e.g. LDPC decoder) configured to decode data carried on data symbols of the received signal based on CSI values. The CSI scaling module is configured to monitor the performance of the soft decision error corrector and in response to determining the performance of the soft decision error corrector is below a predetermined level, dynamically select a new CSI scaling factor based on the performance of the soft decision error corrector.
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公开(公告)号：US10862624B2
公开(公告)日：2020-12-08
申请号：US16457954
申请日：2019-06-29
Applicant: Imagination Technologies Limited
Inventor： Filipe Carvalho , Paul Murrin
Abstract: Channel state information (CSI) scaling modules for use in a demodulator configured to demodulate a signal received over a transmission channel, the demodulator comprising a soft decision error corrector (e.g. LDPC decoder) configured to decode data carried on data symbols of the received signal based on CSI values. The CSI scaling module is configured to monitor the performance of the soft decision error corrector and in response to determining the performance of the soft decision error corrector is below a predetermined level, dynamically select a new CSI scaling factor based on the performance of the soft decision error corrector.
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公开(公告)号：US10050811B2
公开(公告)日：2018-08-14
申请号：US14505674
申请日：2014-10-03
Applicant: Imagination Technologies Limited
Inventor： Paul Murrin
Abstract: Distortion caused by spurious components in a determined channel impulse response (CIR) is reduced. In an OFDM (orthogonal frequency-division multiplexing) system pilot signals are applied to different subcarriers of different symbols in accordance with a pilot transmission scheme. Channel estimates are determined by time-interpolation for some of the data slots of the received signal which do not already include a pilot signal. For each of a sequence of symbols, a respective Inverse Fast Fourier Transform is performed on the pilot signals and interpolated channel estimates in the data slots of that symbol, thereby determining a sequence of estimated CIRs for the sequence of symbols. Spurious channel components will vary across the sequence of estimated CIRs, whereas the true channel peaks will tend not to significantly vary across the sequence of estimated CIRs. Therefore the sequence of estimated CIRs can be filtered (e.g. with a low-pass filter) to attenuate the spurious components, thereby determining a CIR for the signal for which the distortion caused by the spurious components is reduced.
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Patent Agency Ranking
公开(公告)号：US20180205588A1
公开(公告)日：2018-07-19
申请号：US15921462
申请日：2018-03-14
Applicant: Imagination Technologies Limited
Inventor： Mohammed Alloulah , Paul Murrin , Alamo Spaargaren
CPC classification number: H04L27/2665 , H04L25/022 , H04L25/0224 , H04L25/03006 , H04L25/03159 , H04L27/265 , H04L27/2675 , H04L27/2695
Abstract: Methods and OFDM receivers for decoding an OFDM signal include estimating a channel impulse response from a pilot-dense symbol of the OFDM signal for each of a plurality of potential FFT window positions; determining a noise floor of each of the channel impulse responses; selecting the potential window position corresponding to the channel impulse response with the lowest noise floor as an optimum FFT window position; and decoding symbols of the OFDM signal using the optimum FFT window position.
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公开(公告)号：US09819528B2
公开(公告)日：2017-11-14
申请号：US15181687
申请日：2016-06-14
Applicant: Imagination Technologies Limited
Inventor： Mohammed El-Hajjar , Paul Murrin , Adrian J. Anderson
CPC classification number: H04L27/2647 , H03M13/41 , H04L1/0054 , H04L1/06 , H04L1/0618 , H04L25/067 , H04L27/38
Abstract: Methods and apparatus for efficient demapping of constellations are described. In an embodiment, these methods may be implemented within a digital communications receiver, such as a Digital Terrestrial Television receiver. The method reduces the number of distance metric calculations which are required to calculate soft information in the demapper by locating the closest constellation point to the received symbol. This closest constellation point is identified based on a comparison of distance metrics which are calculated parallel to either the I- or Q-axis. The number of distance metric calculations may be reduced still further by identifying a local minimum constellation point for each bit in the received symbol and these constellation points are identified using a similar method to the closest constellation point. Where the system uses rotated constellations, the received symbol may be unrotated before any constellation points are identified.
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公开(公告)号：US09660677B2
公开(公告)日：2017-05-23
申请号：US14990571
申请日：2016-01-07
Applicant: Imagination Technologies Limited
Inventor： Paul Murrin
CPC classification number: H04B1/10 , H04B7/0626 , H04B17/20 , H04B17/309 , H04B17/354 , H04L1/206 , H04L5/0007 , H04L25/02 , H04L27/2647
Abstract: A method of rejecting impulsive noise in an OFDM receiver is described. The impulsive noise is rejected using channel state information (CSI) and is performed in the frequency domain. A noise power estimate (furthermore referred to as a noise value) is measured for a single OFDM symbol and compared to a threshold value, which may be generated based on a short-term average of OFDM symbols not corrupted by impulsive noise or predicted based on a small number of previously measured OFDM symbols not corrupted by impulsive noise. If the noise estimate for the particular OFDM symbol exceeds the threshold value, the CSI for that symbol is derated (i.e. modified) to reduce the influence of the information from this symbol on the decoding process.
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公开(公告)号：US20160283235A1
公开(公告)日：2016-09-29
申请号：US15079269
申请日：2016-03-24
Applicant: Imagination Technologies Limited
Inventor： Paul Murrin , Gareth Davies , Adrian J. Anderson
CPC classification number: G06F9/30098 , G06F15/167 , G06F15/76
Abstract: A processing system includes a program processor for executing a program, and a dedicated processor for executing operations of a particular type (e.g. vector processing operations). The program processor uses an interfacing module and a group of two or more register banks to offload operations of the particular type to the dedicated processor for execution thereon. Whilst the dedicated processor is accessing one register bank for executing a current operation, the interfacing module can concurrently load data for a subsequent operation into a different one of the register banks. The use of multiple register banks allows the dedicated processor to spend a greater proportion of its time executing operations.
Abstract translation: 处理系统包括用于执行程序的程序处理器和用于执行特定类型（例如向量处理操作）的操作的专用处理器。 程序处理器使用接口模块和一组两个或多个寄存器组来将特定类型的操作卸载到专用处理器以便在其上执行。 当专用处理器访问一个寄存器组以执行当前操作时，接口模块可以同时将用于后续操作的数据加载到不同的寄存器组中。 使用多个寄存器组允许专用处理器花费更多的时间执行操作。
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公开(公告)号：US20220075723A1
公开(公告)日：2022-03-10
申请号：US17529954
申请日：2021-11-18
Applicant: Imagination Technologies Limited
Inventor： Paul Murrin , Adrian J. Anderson , Mohammed El-Hajjar
Abstract: Tile based interleaving and de-interleaving of row-column interleaved data is described. In one example, the de-interleaving is divided into two memory transfer stages, the first from an on-chip memory to a DRAM and the second from the DRAM to an on-chip memory. Each stage operates on part of a row-column interleaved block of data and re-orders the data items, such that the output of the second stage comprises de-interleaved data. In the first stage, data items are read from the on-chip memory according to a non-linear sequence of memory read addresses and written to the DRAM. In the second stage, data items are read from the DRAM according to bursts of linear address sequences which make efficient use of the DRAM interface and written back to on-chip memory according to a non-linear sequence of memory write addresses.
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