公开(公告)号：US09608201B2

公开(公告)日：2017-03-28

申请号：US15181733

申请日：2016-06-14

Applicant: Infineon Technologies AG

Inventor： Carsten von Koblinski ,  Volker Strutz ,  Manfred Engelhardt

IPC: H01L23/31 ,  H01L43/14 ,  H01L21/78 ,  H01L21/84 ,  H01L27/12 ,  H01L27/22 ,  H01L43/06 ,  H01L43/12 ,  H01L23/00 ,  H01L43/04

CPC classification number: H01L43/14 ,  H01L21/78 ,  H01L21/84 ,  H01L23/3121 ,  H01L23/3171 ,  H01L23/3178 ,  H01L23/3185 ,  H01L24/06 ,  H01L27/12 ,  H01L27/22 ,  H01L43/04 ,  H01L43/065 ,  H01L43/12 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/73265 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: In one embodiment, a method of forming a current sensor device includes forming a device region comprising a magnetic sensor within and/or over a semiconductor substrate. The device region is formed adjacent a front side of the semiconductor substrate. The back side of the semiconductor substrate is attached over an insulating substrate, where the back side is opposite the front side. Sidewalls of the semiconductor substrate are exposed by dicing the semiconductor substrate from the front side without completely dicing the insulating substrate. An isolation liner is formed over all of the exposed sidewalls of the semiconductor substrate. The isolation liner and the insulating substrate include a different material. The method further includes separating the insulating substrate to form diced chips, removing at least a portion of the isolation liner from over a top surface of the device region, and forming contacts over the top surface of the device region.

公开(公告)号：US09481563B2

公开(公告)日：2016-11-01

申请号：US14644937

申请日：2015-03-11

Applicant: Infineon Technologies AG

Inventor： Manfred Engelhardt ,  Martin Zgaga

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81B3/001 ,  B81B3/0051 ,  B81C1/00531 ,  B81C1/00626 ,  B81C2201/0112 ,  B81C2201/0132 ,  H01L21/30655

Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes a micro-mechanical structure and a semiconductor material arranged over the micro-mechanical structure. A side surface of the semiconductor material includes a first region and a second region. The first region has an undulation, and the second region is a peripheral region of the side surface and decreases towards the micro-mechanical structure.

Abstract translation: 根据半导体器件的实施例，半导体器件包括布置在微机械结构上的微机械结构和半导体材料。 半导体材料的侧表面包括第一区域和第二区域。 第一区域具有起伏，第二区域是侧表面的周边区域，朝向微机械结构减小。

公开(公告)号：US20160111255A1

公开(公告)日：2016-04-21

申请号：US14977625

申请日：2015-12-21

Applicant: Infineon Technologies AG

Inventor： Manfred Engelhardt ,  Gudrun Stranzl ,  Markus Zundel ,  Hubert Maier

IPC: H01J37/32

CPC classification number: H01J37/32009 ,  B28D5/00 ,  H01J2237/334 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834

Abstract: Various methods and apparatuses are provided relating to separation of a substrate into a plurality of parts. For example, first a partial separation is performed and then the partially separated substrate is completely separated into a plurality of parts.

公开(公告)号：US20150147850A1

公开(公告)日：2015-05-28

申请号：US14088523

申请日：2013-11-25

Applicant: Infineon Technologies AG

Inventor： Gudrun Stranzl ,  Martin Zgaga ,  Rainer Leuschner ,  Bernhard Goller ,  Bernhard Boche ,  Manfred Engelhardt ,  Hermann Wendt ,  Bernd Noehammer ,  Karl Mayer ,  Michael Roesner ,  Monika Cornelia Voerckel

IPC: H01L21/82 ,  H01L21/283 ,  H01L21/265 ,  H01L23/00

CPC classification number: H01L21/6835 ,  H01L21/0331 ,  H01L21/283 ,  H01L21/2855 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/6836 ,  H01L21/76895 ,  H01L21/78 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2924/12042 ,  H01L2924/13055 ,  H01L2924/0001

Abstract: Methods for processing a semiconductor workpiece can include providing a semiconductor workpiece that includes one or more kerf regions; forming one or more trenches in the workpiece by removing material from the one or more kerf regions from a first side of the workpiece; mounting the workpiece with the first side to a carrier; thinning the workpiece from a second side of the workpiece; and forming a metallization layer over the second side of the workpiece.

Abstract translation: 用于处理半导体工件的方法可以包括提供包括一个或多个切口区域的半导体工件; 通过从所述工件的第一侧移除来自所述一个或多个切割区域的材料，在所述工件中形成一个或多个沟槽; 将具有第一侧的工件安装到载体上; 从工件的第二侧使工件变薄; 以及在所述工件的第二侧上形成金属化层。

公开(公告)号：US20140327003A1

公开(公告)日：2014-11-06

申请号：US13886283

申请日：2013-05-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Edward FUERGUT ,  Irmgard Escher-Poeppel ,  Manfred Engelhardt ,  Hans-Joerg Timme ,  Hannes Eder

IPC: H01L21/66 ,  H01L21/67

CPC classification number: H01L22/24 ,  H01L21/568 ,  H01L21/67069 ,  H01L21/67253 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/784 ,  H01L22/12 ,  H01L22/26 ,  H01L22/30 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/94 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2224/82 ,  H01L2924/00

Abstract: A method of processing a plurality of packaged electronic chips being connected to one another in a common substrate is provided, wherein the method comprises etching the electronic chips, detecting information indicative of an at least partial removal of an indicator structure following an exposure of the indicator structure embedded within at least a part of the electronic chips and being exposed after the etching has removed chip material above the indicator structure, and adjusting the processing upon detecting the information indicative of the at least partial removal of the indicator structure.

Abstract translation: 提供一种处理在公共基板中彼此连接的多个封装电子芯片的方法，其中所述方法包括蚀刻所述电子芯片，检测指示在所述指示符的曝光之后至少部分移除指示符结构的信息 嵌入在电子芯片的至少一部分内并且在蚀刻之后暴露出指示器结构之上的芯片材料的结构，以及在检测到指示结构的至少部分移除的信息时调整处理。

公开(公告)号：US20140291779A1

公开(公告)日：2014-10-02

申请号：US13851691

申请日：2013-03-27

Applicant: Infineon Technologies AG

Inventor： Manfred Engelhardt ,  Martin Zgaga

IPC: B81C1/00 ,  B81B3/00

CPC classification number: B81B3/001 ,  B81B3/0051 ,  B81C1/00531 ,  B81C1/00626 ,  B81C2201/0112 ,  B81C2201/0132 ,  H01L21/30655

Abstract: A method includes a step of performing a time multiplexed etching process, wherein the last etching step of the time multiplexed etching process is of a first time duration. After performing the time multiplexed etching process, an etching step having a second time duration is performed, wherein the second time duration is greater than the first time duration.

Abstract translation: 一种方法包括执行时间复用蚀刻工艺的步骤，其中时间复用蚀刻工艺的最后一个蚀刻步骤是第一持续时间。 在执行时间复用蚀刻处理之后，执行具有第二持续时间的蚀刻步骤，其中第二持续时间大于第一持续时间。

公开(公告)号：US10074566B2

公开(公告)日：2018-09-11

申请号：US15596961

申请日：2017-05-16

Applicant: Infineon Technologies AG

Inventor： Johannes Baumgartl ,  Manfred Engelhardt ,  Oliver Hellmund ,  Iris Moder ,  Ingo Muri

IPC: H01L21/301 ,  H01L21/78 ,  H01L21/306 ,  H01L21/311 ,  H01L21/683 ,  H01L21/768 ,  H01L23/528 ,  H01L29/06 ,  H01L21/02 ,  H01L21/304 ,  H01L21/82

CPC classification number: H01L21/78 ,  H01L21/02013 ,  H01L21/304 ,  H01L21/3043 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/6835 ,  H01L21/76895 ,  H01L21/82 ,  H01L23/528 ,  H01L29/0657 ,  H01L29/0834 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/861 ,  H01L2221/68327 ,  H01L2221/6834

Abstract: A method for forming a plurality of semiconductor devices includes forming a plurality of trenches extending from a first lateral surface of a semiconductor wafer towards a second lateral surface of the semiconductor wafer. The method further includes filling a portion of the plurality of trenches with filler material. The method further includes thinning the semiconductor wafer from the second lateral surface of the semiconductor wafer to form a thinned semiconductor wafer. The method further includes forming a back side metallization layer structure on a plurality of semiconductor chip regions of the semiconductor wafer after thinning the semiconductor wafer. The method further includes removing a part of the filler material from the plurality of trenches after forming the back side metallization layer structure to obtain the plurality of semiconductor devices.

公开(公告)号：US09793129B2

公开(公告)日：2017-10-17

申请号：US14717780

申请日：2015-05-20

Applicant: Infineon Technologies AG

Inventor： Manfred Engelhardt ,  Michael Roesner ,  Georg Ehrentraut

IPC: H01L21/3065 ,  H01L21/78 ,  H01J37/32 ,  H01L21/67

CPC classification number: H01L21/3065 ,  H01J37/32642 ,  H01J37/32651 ,  H01L21/67092 ,  H01L21/78

Abstract: A segmented edge protection shield for plasma dicing a wafer. The segmented edge protection shield includes an outer structure and a plurality of plasma shield edge segments. The outer structure defines an interior annular edge configured to correspond to the circumferential edge of the wafer. Each one of the plurality of plasma shield edge segments is defined by an inner edge and side edges. The inner edge is interior to and concentric to the annular edge of the outer structure. The side edges extend between the inner edge and the annular edge.

公开(公告)号：US20170032986A1

公开(公告)日：2017-02-02

申请号：US14812784

申请日：2015-07-29

Applicant: Infineon Technologies AG

Inventor： Manfred Engelhardt

IPC: H01L21/67 ,  H01L21/3065

CPC classification number: H01L21/67069 ,  H01J37/3211 ,  H01J37/3222 ,  H01J37/32284 ,  H01J37/32458 ,  H01L21/3065 ,  H01L21/67115

Abstract: A plasma system includes a plasma chamber comprising a chamber wall with a first focal line and a second focal line disposed within the chamber wall. A first antenna is disposed within the plasma chamber at the first focal line. The chamber wall is configured to focus radiation from the first antenna on to the second focal line.

Abstract translation: 等离子体系统包括等离子体室，其包括具有第一焦线的室壁和设置在室壁内的第二焦线。 第一天线设置在第一焦线处的等离子体室内。 室壁被配置为将来自第一天线的辐射聚焦到第二焦线。

公开(公告)号：US20160240366A1

公开(公告)日：2016-08-18

申请号：US14624205

申请日：2015-02-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Manfred Engelhardt ,  Hannes Eder

IPC: H01L21/02 ,  H01L21/324 ,  H01L21/66 ,  H01L21/3065

CPC classification number: H01L21/3065 ,  H01L21/304 ,  H01L21/67103 ,  H01L21/67248 ,  H01L21/6835 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2221/6834

Abstract: A method of thinning a wafer includes thinning the wafer using a grinding process. The wafer, after the grinding processing, has a first non-uniformity in thickness. The thinned wafer is etched using a plasma process. The wafer after the etching processing has a second non-uniformity in thickness. The second non-uniformity is less than the first non-uniformity.

Abstract translation: 削薄晶片的方法包括使用研磨工艺来稀薄晶片。 在研磨处理之后，晶片具有第一不均匀的厚度。 使用等离子体工艺蚀刻薄的晶片。 蚀刻处理后的晶片具有第二厚度不均匀性。 第二个不均匀度小于第一个不均匀性。