公开(公告)号：US20240049450A1

公开(公告)日：2024-02-08

申请号：US18381119

申请日：2023-10-17

Applicant: Intel Corporation

Inventor： Travis W. LAJOIE ,  Abhishek A. SHARMA ,  Van H. LE ,  Chieh-Jen KU ,  Pei-Hua WANG ,  Jack T. KAVALIEROS ,  Bernhard SELL ,  Tahir GHANI ,  Gregory GEORGE ,  Akash GARG ,  Allen B. GARDINER ,  Shem OGADHOH ,  Juan G. ALZATE VINASCO ,  Umut ARSLAN ,  Fatih HAMZAOGLU ,  Nikhil MEHTA ,  Jared STOEGER ,  Yu-Wen HUANG ,  Shu ZHOU

IPC: H10B12/00 ,  H01L27/12

CPC classification number: H10B12/315 ,  H01L27/1218 ,  H01L27/1222 ,  H01L27/1225 ,  H01L28/82 ,  H01L27/1248 ,  H01L27/1255 ,  H01L28/55 ,  H01L28/65 ,  H01L27/124 ,  H10B12/312 ,  H10B12/0335

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate. A first capacitor includes a first top plate and a first bottom plate above the substrate. The first top plate is coupled to a first metal electrode within an inter-level dielectric (ILD) layer to access the first capacitor. A second capacitor includes a second top plate and a second bottom plate, where the second top plate is coupled to a second metal electrode within the ILD layer to access the second capacitor. The second metal electrode is disjoint from the first metal electrode. The first capacitor is accessed through the first metal electrode without accessing the second capacitor through the second metal electrode. Other embodiments may be described and/or claimed.

公开(公告)号：US20220199807A1

公开(公告)日：2022-06-23

申请号：US17129867

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Noriyuki SATO ,  Sarah ATANASOV ,  Abhishek A. Sharma ,  Bernhard SELL ,  Chieh-Jen KU ,  Elliot N. TAN ,  Hui Jae YOO ,  Travis W. LAJOIE ,  Van H. LE ,  Pei-Hua WANG ,  Jason PECK ,  Tobias BROWN-HEFT

IPC: H01L29/66 ,  H01L27/092 ,  H01L21/8234

Abstract: Thin film transistors fabricated using a spacer as a fin are described. In an example, a method of forming a fin transistor structure includes patterning a plurality of backbone pillars on a semiconductor substrate. The method may then include conformally depositing a spacer layer over the plurality of backbone pillars and the semiconductor substrate. A spacer etch of the spacer layer is then performed to leave a sidewall of the spacer layer on a backbone pillar to form a fin of the fin transistor structure. Other embodiments may be described and claimed

公开(公告)号：US20210366821A1

公开(公告)日：2021-11-25

申请号：US17398933

申请日：2021-08-10

Applicant: Intel Corporation

Inventor： Travis LAJOIE ,  Abhishek SHARMA ,  Juan ALZATE-VINASCO ,  Chieh-Jen KU ,  Shem OGADHOH ,  Allen GARDINER ,  Blake LIN ,  Yih WANG ,  Pei-Hua WANG ,  Jack T. KAVALIEROS ,  Bernhard SELL ,  Tahir GHANI

IPC: H01L23/522 ,  H01L49/02 ,  H01L27/108 ,  H01L23/532

Abstract: An interconnect structure is disclosed. The interconnect structure includes a first metal interconnect in a bottom dielectric layer, a via that extends through a top dielectric layer, a metal plate, an intermediate dielectric layer, and an etch stop layer, and a metal in the via to extend through the top dielectric layer, the metal plate, the intermediate dielectric layer and the etch stop layer to the top surface of the first metal interconnect. The metal plate is coupled to an MIM capacitor that is parallel to the via. The second metal interconnect is on top of the metal in the via.

公开(公告)号：US20210125992A1

公开(公告)日：2021-04-29

申请号：US16645362

申请日：2017-12-22

Applicant: Intel Corporation

Inventor： Travis LAJOIE ,  Tahir GHANI ,  Jack T. KAVALIEROS ,  Shem O. OGADHOH ,  Yih WANG ,  Bernhard SELL ,  Allen GARDINER ,  Blake LIN ,  Juan G. ALZATE VINASCO ,  Pei-Hua WANG ,  Chieh-Jen KU ,  Abhishek A. SHARMA

IPC: H01L27/108 ,  H01L27/12

Abstract: Embodiments herein describe techniques for a semiconductor device having an interconnect structure above a substrate. The interconnect structure may include an inter-level dielectric (ILD) layer and a separation layer above the ILD layer. A first conductor and a second conductor may be within the ILD layer. The first conductor may have a first physical configuration, and the second conductor may have a second physical configuration different from the first physical configuration. Other embodiments may be described and/or claimed.

公开(公告)号：US20190319121A1

公开(公告)日：2019-10-17

申请号：US16393290

申请日：2019-04-24

Applicant: Intel Corporation

Inventor： Bernhard SELL

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/417 ,  H01L29/78 ,  H01L27/108 ,  H01L27/088 ,  H01L29/786 ,  H01L29/165 ,  H01L29/08 ,  H01L29/10 ,  H01L29/49 ,  H01L29/51 ,  H01L29/06 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8234 ,  H01L29/16 ,  H01L27/12

Abstract: Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.

公开(公告)号：US20150108567A1

公开(公告)日：2015-04-23

申请号：US14581498

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Bernhard SELL ,  Oleg GOLONZKA

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L23/535 ,  H01L21/28052 ,  H01L21/28123 ,  H01L21/76805 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53266 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/4175 ,  H01L29/4925 ,  H01L29/66666 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an IID disposed on a top surface of a metal gate disposed on the substrate.

Abstract translation: 描述形成微电子器件的方法和相关结构。 这些方法可以包括形成包括设置在基板的源极/漏极接触件上的第一接触金属和设置在第一接触金属的顶表面上的第二接触金属的结构，其中第二接触金属设置在设置的IID内 在设置在基板上的金属栅极的顶面上。