公开(公告)号：US20220076995A1

公开(公告)日：2022-03-10

申请号：US17530777

申请日：2021-11-19

Applicant: Intel Corporation

Inventor： Kevin Lin ,  Christopher J. Jezewski

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/528

Abstract: Integrated circuit (IC) interconnect lines having line breaks and line bridges within one interconnect level that are based on a single lithographic mask pattern. Multi-patterning may be employed to define a grating structure of a desired pitch in a first mask layer. Breaks and bridges between the grating structures may be derived from a second mask layer through a process-based selective occlusion of openings defined in the second mask layer that are below a threshold minimum lateral width. Portions of the grating structure underlying openings defined in the second mask layer that exceed the threshold minimum lateral width are removed. Trenches in an underlayer may then be etched based on a union of the remainder of the grating structure and the occluded openings in the second mask layer. The trenches may then be backfilled to form the interconnect lines.

公开(公告)号：US20200321246A1

公开(公告)日：2020-10-08

申请号：US16651295

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Kevin Lin ,  Christopher J. Jezewski

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/528

Abstract: Integrated circuit (IC) interconnect lines having line breaks and line bridges within one interconnect level that are based on a single lithographic mask pattern. Multi-patterning may be employed to define a grating structure of a desired pitch in a first mask layer. Breaks and bridges between the grating structures may be derived from a second mask layer through a process-based selective occlusion of openings defined in the second mask layer that are below a threshold minimum lateral width. Portions of the grating structure underlying openings defined in the second mask layer that exceed the threshold minimum lateral width are removed. Trenches in an underlayer may then be etched based on a union of the remainder of the grating structure and the occluded openings in the second mask layer. The trenches may then be backfilled to form the interconnect lines.

公开(公告)号：US10529660B2

公开(公告)日：2020-01-07

申请号：US16318643

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Jessica M. Torres ,  Jeffery D. Bielefeld ,  Mauro J. Kobrinsky ,  Christopher J. Jezewski ,  Gopinath Bhimarasetti

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L21/02 ,  H01L21/033 ,  H01L21/311

Abstract: Pore-filled dielectric materials for semiconductor structure fabrication, and methods of fabricating pore-filled dielectric materials for semiconductor structure fabrication, are described. In an example, a method of fabricating a pore-filled dielectric material for semiconductor structure fabrication includes forming a trench in a material layer. The method also includes filling the trench with a porous dielectric material using a spin-on deposition process. The method also includes filling pores of the porous dielectric material with a metal-containing material using an atomic layer deposition (ALD) process.

公开(公告)号：US20190326214A1

公开(公告)日：2019-10-24

申请号：US16465119

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Kevin Lin ,  Christopher J. Jezewski ,  Richard F. Vreeland ,  Tristan A. Tronic

IPC: H01L23/522 ,  H01L21/768 ,  H01L27/01 ,  H01L49/02

Abstract: Methods/structures of forming thin film resistors using interconnect liner materials are described. Those methods/structures may include forming a first liner in a first trench, wherein the first trench is disposed in a dielectric layer that is disposed on a substrate. Forming a second liner in a second trench, wherein the second trench is adjacent the first trench, forming an interconnect material on the first liner in the first trench, adjusting a resistance value of the second liner, forming a first contact structure on a top surface of the interconnect material, and forming a second contact structure on the second liner.

公开(公告)号：US20190259844A1

公开(公告)日：2019-08-22

申请号：US15899590

申请日：2018-02-20

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Tahir Ghani ,  Jack T. Kavalieros ,  Gilbert Dewey ,  Van H. Le ,  Lawrence D. Wong ,  Christopher J. Jezewski

IPC: H01L29/417 ,  H01L29/786 ,  H01L23/29 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

Abstract: Disclosed herein are transistor electrode-channel arrangements, and related methods and devices. For example, in some embodiments, a transistor electrode-channel arrangement may include a channel material, source/drain electrodes provided over the channel material, and a sealant at least partially enclosing one or more of the source/drain electrodes, wherein the sealant includes one or more metallic conductive materials.

公开(公告)号：US09911694B2

公开(公告)日：2018-03-06

申请号：US15201420

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Christopher J. Jezewski ,  Jasmeet S. Chawla

IPC: H01L29/40 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L21/311 ,  H01L21/033

CPC classification number: H01L23/528 ,  H01L21/02126 ,  H01L21/0337 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the invention describe low capacitance interconnect structures for semiconductor devices and methods for manufacturing such devices. According to an embodiment of the invention, a low capacitance interconnect structure comprises an interlayer dielectric (ILD). First and second interconnect lines are disposed in the ILD in an alternating pattern. The top surfaces of the first interconnect lines may be recessed below the top surfaces of the second interconnect lines. Increases in the recess of the first interconnect lines decreases the line-to-line capacitance between neighboring interconnects. Further embodiments include utilizing different dielectric materials as etching caps above the first and second interconnect lines. The different materials may have a high selectivity over each other during an etching process. Accordingly, the alignment budget for contacts to individual interconnect lines is increased.

公开(公告)号：US09406615B2

公开(公告)日：2016-08-02

申请号：US14139970

申请日：2013-12-24

Applicant: INTEL CORPORATION

Inventor： Christopher J. Jezewski ,  David J. Michalak ,  Kanwal Jit Singh ,  Alan M. Myers

IPC: H01L23/48 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5329 ,  H01L21/02203 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/7682 ,  H01L21/76822 ,  H01L21/76826 ,  H01L21/76838 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Techniques are disclosed for forming interconnects in porous dielectric materials. In accordance with some embodiments, the porosity of a host dielectric layer may be reduced temporarily by stuffing its pores with a sacrificial pore-stuffing material, such as titanium nitride (TiN), titanium dioxide (TiO2), or other suitable sacrificial material having a high etch selectivity compared to the metallization and dielectric material of the interconnect. After interconnect formation within the stuffed dielectric layer, the sacrificial pore-stuffing material can be removed from the pores of the host dielectric. In some cases, removal and curing can be performed with minimal or otherwise negligible effect on the dielectric constant (κ-value), leakage performance, and/or time-dependent dielectric breakdown (TDDB) properties of the host dielectric layer. Some embodiments can be utilized, for example, in processes involving atomic layer deposition (ALD)-based and/or chemical vapor deposition (CVD)-based backend metallization of highly porous, ultra-low-κ (ULK) dielectric materials.

Abstract translation: 公开了用于在多孔电介质材料中形成互连的技术。 根据一些实施例，可以通过用诸如氮化钛（TiN），二氧化钛（TiO 2）或其它合适的牺牲材料的牺牲孔填充材料填充其孔来临时减小主介质层的孔隙率， 与互连的金属化和介电材料相比，具有高蚀刻选择性。 在填充电介质层内形成互连之后，可以从主电介质的孔中去除牺牲孔填充材料。 在某些情况下，可以对主介电层的介电常数（κ值），泄漏性能和/或时间依赖的介电击穿（TDDB）性能产生最小或其他可忽略的影响来进行去除和固化。 一些实施例可以用于例如涉及基于原子层沉积（ALD）的和/或化学气相沉积（CVD）的高多孔，超低κ（ULK）电介质材料的后端金属化的工艺。

公开(公告)号：US09379010B2

公开(公告)日：2016-06-28

申请号：US14163323

申请日：2014-01-24

Applicant: Intel Corporation

Inventor： Christopher J. Jezewski ,  Jasmeet S. Chawla ,  Kanwal Jit Singh ,  Alan M. Myers ,  Elliot N. Tan ,  Richard E. Schenker

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/7688 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76886 ,  H01L21/76897 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Processes for forming interconnection layers having tight pitch interconnect structures within a dielectric layer, wherein trenches and vias used to form interconnect structures have relatively low aspect ratios prior to metallization. The low aspect ratios may reduce or substantially eliminate the potential of voids forming within the metallization material when it is deposited. Embodiments herein may achieve such relatively low aspect ratios through processes that allow for the removal of structures, which are utilized to form the trenches and the vias, prior to metallization.

Abstract translation: 用于在电介质层内形成具有窄间距互连结构的互连层的工艺，其中用于形成互连结构的沟槽和通孔在金属化之前具有相对低的纵横比。 当沉积时，低纵横比可以减少或基本上消除在金属化材料内形成的空隙的潜力。 本文的实施例可以通过允许在金属化之前去除用于形成沟槽和通孔的结构的工艺来实现这种相对低的纵横比。

公开(公告)号：US09343411B2

公开(公告)日：2016-05-17

申请号：US13753245

申请日：2013-01-29

Applicant: INTEL CORPORATION

Inventor： Christopher J. Jezewski ,  Mauro J. Kobrinsky ,  Daniel Pantuso ,  Siddharth B. Bhingarde ,  Michael P. O'Day

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H01L23/538 ,  H01L23/62 ,  H01L23/00 ,  H01L23/29

CPC classification number: H01L23/562 ,  H01L23/293 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/535 ,  H01L23/5381 ,  H01L23/5386 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Techniques and structure are disclosed for enhancing fracture resistance of back-end interconnects and other such interconnect structures by increasing via density. Increased via density can be provided, for example, within the filler/dummified portion(s) of adjacent circuit layers within a die. In some cases, an electrically isolated (floating) filler line of an upper circuit layer may include a via which lands on a floating filler line of a lower circuit layer in a region corresponding to where the filler lines cross/intersect. In some such cases, the floating filler line of the upper circuit layer may be formed as a dual-damascene structure including such a via. In some embodiments, a via similarly may be provided between a floating filler line of the upper circuit layer and a sufficiently electrically isolated interconnect line of the lower circuit layer. The techniques/structure can be used to provide mechanical integrity for the die.

Abstract translation: 公开了通过增加通孔密度来提高后端互连和其它这种互连结构的抗断裂性的技术和结构。 可以例如在模具内的相邻电路层的填充/加工部分内提供通孔密度的增加。 在一些情况下，上电路层的电隔离（浮置）填充线可以包括在对应于填充线交叉/相交的区域中的下电路层的浮动填充线上的通孔。 在一些这样的情况下，上电路层的浮动填充线可以形成为包括这种通孔的双镶嵌结构。 在一些实施例中，可以在上电路层的浮动填充线和下电路层的充分电隔离的互连线之间提供通孔。 技术/结构可用于为模具提供机械完整性。

公开(公告)号：US12170319B2

公开(公告)日：2024-12-17

申请号：US17033362

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Kevin Cook ,  Anand S. Murthy ,  Gilbert Dewey ,  Nazila Haratipour ,  Ralph Thomas Troeger ,  Christopher J. Jezewski ,  I-Cheng Tung

IPC: H01L29/417 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/40 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

Abstract: Embodiments disclosed herein include complementary metal-oxide-semiconductor (CMOS) devices and methods of forming CMOS devices. In an embodiment, a CMOS device comprises a first transistor with a first conductivity type, where the first transistor comprises a first source region and a first drain region, and a first metal over the first source region and the first drain region. In an embodiment, the CMOS device further comprises a second transistor with a second conductivity type opposite form the first conductivity type, where the second transistor comprises a second source region and a second drain region, a second metal over the second source region and the second drain region, and the first metal over the second metal.