公开(公告)号：US12278204B2

公开(公告)日：2025-04-15

申请号：US17404870

申请日：2021-08-17

Applicant: Intel Corporation

Inventor： Charles H. Wallace ,  Hossam A. Abdallah ,  Elliot N. Tan ,  Swaminathan Sivakumar ,  Oleg Golonzka ,  Robert M. Bigwood

IPC: G03F7/16 ,  G03F1/36 ,  G03F1/50 ,  G03F1/70 ,  G03F7/00 ,  G03F7/40 ,  H01L21/02 ,  H01L21/027 ,  H01L21/263 ,  H01L21/306 ,  H01L21/308 ,  H01L23/00 ,  H01L27/02

Abstract: Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may be arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern. The pattern decomposition techniques may be integrated into any number of patterning processes, such as litho-freeze-litho-etch and litho-etch-litho-etch patterning processes.

公开(公告)号：US12218052B2

公开(公告)日：2025-02-04

申请号：US18384582

申请日：2023-10-27

Applicant: Intel Corporation

Inventor： Richard E. Schenker ,  Robert L Bristol ,  Kevin L. Lin ,  Florian Gstrein ,  James M. Blackwell ,  Marie Krysak ,  Manish Chandhok ,  Paul A Nyhus ,  Charles H. Wallace ,  Curtis W. Ward ,  Swaminathan Sivakumar ,  Elliot N. Tan

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/088 ,  H01L29/78

Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

公开(公告)号：US12080781B2

公开(公告)日：2024-09-03

申请号：US17129867

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Noriyuki Sato ,  Sarah Atanasov ,  Abhishek A. Sharma ,  Bernhard Sell ,  Chieh-Jen Ku ,  Elliot N. Tan ,  Hui Jae Yoo ,  Travis W. Lajoie ,  Van H. Le ,  Pei-Hua Wang ,  Jason Peck ,  Tobias Brown-Heft

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/092

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L27/0924

Abstract: Thin film transistors fabricated using a spacer as a fin are described. In an example, a method of forming a fin transistor structure includes patterning a plurality of backbone pillars on a semiconductor substrate. The method may then include conformally depositing a spacer layer over the plurality of backbone pillars and the semiconductor substrate. A spacer etch of the spacer layer is then performed to leave a sidewall of the spacer layer on a backbone pillar to form a fin of the fin transistor structure. Other embodiments may be described and claimed.

公开(公告)号：US10409152B2

公开(公告)日：2019-09-10

申请号：US15419147

申请日：2017-01-30

Applicant: INTEL CORPORATION

Inventor： Charles H. Wallace ,  Hossam A. Abdallah ,  Elliot N. Tan ,  Swaminathan Sivakumar ,  Oleg Golonzka ,  Robert M. Bigwood

IPC: G03F1/36 ,  H01L21/027 ,  H01L21/308 ,  G03F1/50 ,  G03F7/20

Abstract: Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may be arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern. The pattern decomposition techniques may be integrated into any number of patterning processes, such as litho-freeze-litho-etch and litho-etch-litho-etch patterning processes.

公开(公告)号：US20240241446A1

公开(公告)日：2024-07-18

申请号：US18620262

申请日：2024-03-28

Applicant: Intel Corporation

Inventor： Marvin Paik ,  Charles H. Wallace ,  Leonard Guler ,  Elliot N. Tan ,  Shengsi Liu ,  Vivek Vishwakarma ,  Izabela Samek ,  Mohammadreza Soleymaniha

IPC: G03F7/20 ,  G03F7/00 ,  H01L21/027

CPC classification number: G03F7/2022 ,  G03F7/2004 ,  G03F7/201 ,  G03F7/70033 ,  G03F7/7005 ,  G03F7/70525 ,  G03F7/7055 ,  G03F7/70725 ,  H01L21/0275

Abstract: Apparatus and methods are disclosed. An example lithography apparatus includes an ultraviolet (UV) source to expose a photoresist layer to UV light; and an extreme ultraviolet (EUV) source coupled to the UV source, the EUV source to expose the photoresist layer to EUV light to via a photomask, a combination of the UV light and the EUV light provide a pattern on the photoresist layer when a developer solution is applied to the photoresist layer.

公开(公告)号：US11373950B2

公开(公告)日：2022-06-28

申请号：US17110215

申请日：2020-12-02

Applicant: Intel Corporation

Inventor： Richard E. Schenker ,  Robert L. Bristol ,  Kevin L. Lin ,  Florian Gstrein ,  James M. Blackwell ,  Marie Krysak ,  Manish Chandhok ,  Paul A. Nyhus ,  Charles H. Wallace ,  Curtis W. Ward ,  Swaminathan Sivakumar ,  Elliot N. Tan

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/088 ,  H01L29/78

Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

公开(公告)号：US11107786B2

公开(公告)日：2021-08-31

申请号：US16692589

申请日：2019-11-22

Applicant: INTEL CORPORATION

Inventor： Charles H. Wallace ,  Hossam A. Abdallah ,  Elliot N. Tan ,  Swaminathan Sivakumar ,  Oleg Golonzka ,  Robert M. Bigwood

IPC: G03F7/20 ,  H01L23/00 ,  G03F7/00 ,  G03F7/40 ,  H01L21/027 ,  G03F1/36 ,  G03F1/70 ,  H01L21/02 ,  H01L21/263 ,  H01L27/02 ,  G03F1/50 ,  G03F7/16 ,  H01L21/306 ,  H01L21/308

Abstract: Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may be arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern. The pattern decomposition techniques may be integrated into any number of patterning processes, such as litho-freeze-litho-etch and litho-etch-litho-etch patterning processes.

公开(公告)号：US10892223B2

公开(公告)日：2021-01-12

申请号：US16346873

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Richard E. Schenker ,  Robert L. Bristol ,  Kevin L. Lin ,  Florian Gstrein ,  James M. Blackwell ,  Marie Krysak ,  Manish Chandhok ,  Paul A. Nyhus ,  Charles H. Wallace ,  Curtis W. Ward ,  Swaminathan Sivakumar ,  Elliot N. Tan

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/088 ,  H01L29/78

Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

公开(公告)号：US09379010B2

公开(公告)日：2016-06-28

申请号：US14163323

申请日：2014-01-24

Applicant: Intel Corporation

Inventor： Christopher J. Jezewski ,  Jasmeet S. Chawla ,  Kanwal Jit Singh ,  Alan M. Myers ,  Elliot N. Tan ,  Richard E. Schenker

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/7688 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76886 ,  H01L21/76897 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Processes for forming interconnection layers having tight pitch interconnect structures within a dielectric layer, wherein trenches and vias used to form interconnect structures have relatively low aspect ratios prior to metallization. The low aspect ratios may reduce or substantially eliminate the potential of voids forming within the metallization material when it is deposited. Embodiments herein may achieve such relatively low aspect ratios through processes that allow for the removal of structures, which are utilized to form the trenches and the vias, prior to metallization.

Abstract translation: 用于在电介质层内形成具有窄间距互连结构的互连层的工艺，其中用于形成互连结构的沟槽和通孔在金属化之前具有相对低的纵横比。 当沉积时，低纵横比可以减少或基本上消除在金属化材料内形成的空隙的潜力。 本文的实施例可以通过允许在金属化之前去除用于形成沟槽和通孔的结构的工艺来实现这种相对低的纵横比。

公开(公告)号：US12150297B2

公开(公告)日：2024-11-19

申请号：US17129869

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Noriyuki Sato ,  Sarah Atanasov ,  Abhishek A. Sharma ,  Bernhard Sell ,  Chieh-Jen Ku ,  Arnab Sen Gupta ,  Matthew V. Metz ,  Elliot N. Tan ,  Hui Jae Yoo ,  Travis W. Lajoie ,  Van H. Le ,  Pei-Hua Wang

IPC: H10B12/00 ,  H01L29/786

Abstract: An integrated circuit (IC) structure in a memory device is described. In an example, the IC structure includes a memory cell including a bitline (BL) extending along a first direction and a channel extending along a second direction above and diagonal to the BL. In the example, a wordline (WL) extends in a third direction perpendicular to the first direction of the BL and intersects with the channel to control a current in the channel along a gated channel length. In some examples, the channel is electrically coupled on a first side to a storage capacitor via a storage node contact (SNC) and on a second side to the BL via a bit line contact (BLC) located on an underside or backside of the channel.