公开(公告)号：US12165928B2

公开(公告)日：2024-12-10

申请号：US17505468

申请日：2021-10-19

Applicant: Intel Corporation

Inventor： Srijit Mukherjee ,  Christopher J. Wiegand ,  Tyler J. Weeks ,  Mark Y. Liu ,  Michael L Hattendorf

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/49 ,  H10B10/00

Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.

公开(公告)号：US11056593B2

公开(公告)日：2021-07-06

申请号：US16631059

申请日：2017-09-12

Applicant: INTEL CORPORATION

Inventor： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Uygar E. Avci ,  Christopher J. Wiegand ,  Anurag Chaudhry ,  Jasmeet S. Chawla ,  Ian A Young

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/18 ,  H01L21/3105 ,  H01L21/8252

Abstract: Techniques are disclosed for forming semiconductor integrated circuits including one or more of source and drain contacts and gate electrodes comprising crystalline alloys including a transition metal. The crystalline alloys help to reduce contact resistance to the semiconductor devices. In some embodiments of the present disclosure, this reduction in contact resistance is accomplished by aligning the work function of the crystalline alloy with the work function of the source and drain regions such that a Schottky barrier height associated with an interface between the crystalline alloys and the source and drain regions is in a range of 0.3 eV or less.

公开(公告)号：US11031545B2

公开(公告)日：2021-06-08

申请号：US16327603

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Kaan Oguz ,  Kevin P. O'Brien ,  Brian S. Doyle ,  Mark L. Doczy ,  Charles C. Kuo ,  Daniel G. Ouellette ,  Christopher J. Wiegand ,  Md Tofizur Rahman ,  Brian Maertz

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: Systems, apparatus, and methods for magnetoresitive memory are described. An apparatus for magnetoresitive memory includes a fixed layer, a free layer, and a tunneling barrier between the fixed layer and the free layer. The free layer is a new alloy consisting of a composition of Cobalt (Co), Iron (Fe), and Boron (B) intermixed with a non-magnetic metal according to a ratio. A thin insert layer of CoFeB may optionally be added between the alloy and the tunneling barrier.

公开(公告)号：US10770651B2

公开(公告)日：2020-09-08

申请号：US16463326

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： MD Tofizur Rahman ,  Christopher J. Wiegand ,  Kaan Oguz ,  Daniel G. Ouellette ,  Brian Maertz ,  Kevin P. O'Brien ,  Mark L. Doczy ,  Brian S. Doyle ,  Oleg Golonzka ,  Tahir Ghani

IPC: H01L27/22 ,  H01L43/02 ,  H01F10/32 ,  H01L43/10 ,  H01L43/12 ,  H01L43/00

Abstract: A material layer stack for a pSTTM device includes a fixed magnetic layer, a tunnel barrier disposed above the fixed magnetic layer and a free layer disposed on the tunnel barrier. The free layer further includes a stack of bilayers where an uppermost bilayer is capped by a magnetic layer including iron and where each of the bilayers in the free layer includes a non-magnetic layer such as Tungsten, Molybdenum disposed on the magnetic layer. In an embodiment, the non-magnetic layers have a combined thickness that is less than 15% of a combined thickness of the magnetic layers in the stack of bilayers. A stack of bilayers including non-magnetic layers in the free layer can reduce the saturation magnetization of the material layer stack for the pSTTM device and subsequently increase the perpendicular magnetic anisotropy.

公开(公告)号：US10411068B2

公开(公告)日：2019-09-10

申请号：US15767127

申请日：2015-11-23

Applicant: Intel Corporation

Inventor： Christopher J. Wiegand ,  Oleg Golonzka ,  Kaan Oguz ,  Kevin P. O'Brien ,  Tofizur Rahman ,  Brian S. Doyle ,  Tahir Ghani ,  Mark L. Doczy

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08

Abstract: Disclosed herein are electrical contacts for magnetoresistive random access memory (MRAM) devices and related memory structures, devices, and methods. For example, and electrical contact for an MRAM device may include: a tantalum region; a barrier region formed of a first material; and a passivation region formed of a second material and disposed between the tantalum region and the barrier region, wherein the second material includes tantalum nitride and is different from the first material.

公开(公告)号：US20180240970A1

公开(公告)日：2018-08-23

申请号：US15755437

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Kaan Oguz ,  Kevin P. O'Brien ,  Christopher J. Wiegand ,  MD Tofizur Rahman ,  Brian S. Doyle ,  Mark L. Doczy ,  Oleg Golonzka ,  Tahir Ghani ,  Justin S. Brockman

IPC: H01L43/12 ,  H01F10/32 ,  H01F41/30 ,  H01L43/08 ,  H01L43/10 ,  G11C11/16

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01F10/3272 ,  H01F10/3286 ,  H01F41/307 ,  H01L43/08 ,  H01L43/10

Abstract: MTJ material stacks, pSTTM devices employing such stacks, and computing platforms employing such pSTTM devices. In some embodiments, perpendicular MTJ material stacks include a multi-layered filter stack disposed between a fixed magnetic layer and an antiferromagnetic layer or synthetic antiferromagnetic (SAF) stack. In some embodiments, non-magnetic layers of the filter stack include at least one of Ta, Mo, Nb, W, or Hf. These transition metals may be in pure form or alloyed with other constituents.

公开(公告)号：US09418898B2

公开(公告)日：2016-08-16

申请号：US14548215

申请日：2014-11-19

Applicant: Intel Corporation

Inventor： Srijit Mukherjee ,  Christopher J. Wiegand ,  Tyler J Weeks ,  Mark Y. Liu ,  Michael L. Hattendorf

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/092 ,  H01L21/28 ,  H01L27/11 ,  H01L21/8238

CPC classification number: H01L21/82385 ,  H01L21/28008 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823821 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/495 ,  H01L29/66477

Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.

Abstract translation: 集成电路包括具有选择性凹陷栅电极的MOSFET。 具有具有减小的电容耦合面积到相邻源极和漏极接触金属化的凹陷栅电极的晶体管与具有非凹陷且具有较大z高度的栅电极的晶体管一起提供。 在实施例中，模拟电路采用具有给定z高度的栅电极的晶体管，而逻辑门采用具有较小z高度的凹陷栅电极的晶体管。 在实施例中，基本上平面的栅电极的子集被选择性地回蚀以基于在电路内的给定晶体管的应用来区分栅电极的高度。

公开(公告)号：US11616192B2

公开(公告)日：2023-03-28

申请号：US16024599

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Tofizur Rahman ,  Christopher J. Wiegand ,  Justin S. Brockman ,  Daniel G. Ouellette ,  Angeline K. Smith ,  Andrew Smith ,  Pedro A. Quintero ,  Juan G. Alzate-Vinasco ,  Oleg Golonzka

IPC: H01L43/02 ,  G11C11/16 ,  H01L27/22 ,  H01L43/12 ,  H01L43/10

Abstract: A memory device includes a perpendicular magnetic tunnel junction (pMTJ) stack, between a bottom electrode and a top electrode. In an embodiment, the pMTJ includes a fixed magnet, a tunnel barrier above the fixed magnet and a free magnet structure on the tunnel barrier. The free magnet structure includes a first free magnet on the tunnel barrier and a second free magnet above the first free magnet, wherein at least a portion of the free magnet proximal to an interface with the free magnet includes a transition metal. The free magnet structure having a transition metal between the first and the second free magnets advantageously improves the switching efficiency of the MTJ, while maintaining a thermal stability of at least 50 kT.

公开(公告)号：US11489112B2

公开(公告)日：2022-11-01

申请号：US16641582

申请日：2017-09-28

Applicant: INTEL CORPORATION

Inventor： Namrata S. Asuri ,  Oleg Golonzka ,  Nathan Strutt ,  Patrick J. Hentges ,  Trinh T. Van ,  Hiten Kothari ,  Ameya S. Chaudhari ,  Matthew J. Andrus ,  Timothy E. Glassman ,  Dragos Seghete ,  Christopher J. Wiegand ,  Daniel G. Ouellette

IPC: H01L45/00 ,  H01L23/528 ,  H01L27/24

Abstract: An apparatus, includes an interconnect, including a conductive material, above a substrate and a resistive random access memory (RRAM) device coupled to the interconnect. The RRAM device includes an electrode structure above the interconnect, where an upper portion of the electrode structure has a first width. The RRAM device further includes a switching layer on the electrode structure, where the switching layer has the first width and an oxygen exchange layer, having a second width less than the first width, on a portion of the switching layer. The RRAM device further includes a top electrode above the oxygen exchange layer, where the top electrode has the second width and an encapsulation layer on a portion of the switching layer, where the switching layer extends along a sidewall of the oxygen exchange layer.

公开(公告)号：US20200152781A1

公开(公告)日：2020-05-14

申请号：US16631059

申请日：2017-09-12

Applicant: INTEL CORPORATION

Inventor： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Uygar E. Avci ,  Christopher J. Wiegand ,  Anurag Chaudhry ,  Jasmeet S. Chawla ,  Ian A. Young

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/49 ,  H01L29/08 ,  H01L29/51 ,  H01L29/66 ,  H01L21/28 ,  H01L29/417

Abstract: Techniques are disclosed for forming semiconductor integrated circuits including one or more of source and drain contacts and gate electrodes comprising crystalline alloys including a transition metal. The crystalline alloys help to reduce contact resistance to the semiconductor devices. In some embodiments of the present disclosure, this reduction in contact resistance is accomplished by aligning the work function of the crystalline alloy with the work function of the source and drain regions such that a Schottky barrier height associated with an interface between the crystalline alloys and the source and drain regions is in a range of 0.3 eV or less.