公开(公告)号：US11107764B2

公开(公告)日：2021-08-31

申请号：US16629936

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Tristan A. Tronic ,  Rajat K. Paul

IPC: H01L23/525 ,  H01L29/20 ,  H01L29/78

Abstract: Group III-V semiconductor fuses and their methods of fabrication are described. In an example, a fuse includes a gallium nitride layer on a substrate. An oxide layer is disposed in a trench in the gallium nitride layer. A first contact is on the gallium nitride layer on a first side of the trench, the first contact comprising indium, gallium and nitrogen. A second contact is on the gallium nitride layer on a second side of the trench, the second side opposite the first side, the second contact comprising indium, gallium and nitrogen. A filament is over the oxide layer in the trench, the filament coupled to the first contact and to the second contact wherein the filament comprises indium, gallium and nitrogen.

公开(公告)号：US20210194459A1

公开(公告)日：2021-06-24

申请号：US16719077

申请日：2019-12-18

Applicant: Intel Corporation

Inventor： Hossein Alavi ,  Ibrahim Ban ,  Telesphor Kamgaing ,  Edris Mohammed ,  Han Wui Then ,  Kevin Obrien ,  Paul Fischer ,  Johanny Escobar Pelaez ,  Ved Gund

IPC: H03H9/54 ,  H03H9/64 ,  H03H9/25 ,  H03H9/58 ,  H03H9/205

Abstract: Techniques are disclosed implementing acoustic wave resonator (AWR) filter architectures to enable integrated solutions requiring significantly less passive components. The primary AWR filter topology leverages the use of parallel resonator branches, each having a relatively narrow bandwidth that may be combined to form an overall broadband filter response. This architecture may be further modified using electronically-controlled switching components to dynamically turn specific branches on or off to tune the filter, thus realizing a programmable broadband solution. Shunt resonators may also be added to the AWR filter topology, which may also be controlled with the use of electronically-controlled switching components to provide further control with respect to roll-off and the location and number of notch frequencies.

公开(公告)号：US11043627B2

公开(公告)日：2021-06-22

申请号：US16304964

申请日：2016-07-01

Applicant: INTEL CORPORATION

Inventor： Han Wui Then ,  Sansaptak Dasgupta ,  Marko Radosavljevic ,  Paul B. Fischer

IPC: H01L41/083 ,  H01L27/20 ,  H01L29/15 ,  H01L29/20 ,  H03H9/17

Abstract: Techniques are disclosed for co-integrating thin-film bulk acoustic resonator (TFBAR, also called FBAR) devices and III-N semiconductor transistor devices. In accordance with some embodiments, a given TFBAR device may include a superlattice structure comprising alternating layers of an epitaxial piezoelectric material, such as aluminum nitride (AlN), and any one, or combination, of other III-N semiconductor materials. For instance, aluminum indium nitride (AlxIn1-xN), aluminum gallium nitride (AlxGa1-xN), or aluminum indium gallium nitride (AlxInyGa1-x-yN) may be interleaved with the AlN, and the particular compositional ratios thereof may be adjusted to customize resonator performance. In accordance with some embodiments, the superlattice layers may be formed via an epitaxial deposition process, allowing for precise control over film thicknesses, in some cases in the range of a few nanometers. In accordance with some embodiments, one or more such TFBAR devices may be formed alongside III-N semiconductor transistor device(s), over a commonly shared semiconductor substrate.

公开(公告)号：US10998260B2

公开(公告)日：2021-05-04

申请号：US16462889

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Sansaptak Dasgupta ,  Marko Radosavljevic ,  Sanaz K. Gardner

IPC: H01L23/522 ,  H01L21/762 ,  H01L21/764 ,  H01L21/768 ,  H01L29/06 ,  H01L23/532

Abstract: Embodiments of the invention include a microelectronic device that includes a substrate, at least one dielectric layer on the substrate and a plurality of conductive lines within the at least one dielectric layer. The microelectronic device also includes an air gap structure that is located below two or more of the plurality of conductive lines.

公开(公告)号：US20200373421A1

公开(公告)日：2020-11-26

申请号：US16419179

申请日：2019-05-22

Applicant: Intel Corporation

Inventor： Nidhi Nidhi ,  Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Paul B. Fischer ,  Rahul Ramaswamy ,  Walid M. Hafez ,  Johann Christian Rode

IPC: H01L29/778 ,  H01L29/20 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00

Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistor arrangements that may reduce nonlinearity of off-state capacitance of the III-N transistors. In various aspects, III-N transistor arrangements limit the extent of access regions of the transistors, compared to conventional implementations, which may limit the depletion of the access regions. Due to the limited extent of the depletion regions of a transistor, the off-state capacitance may exhibit less variability in values across different gate-source voltages and, hence, exhibit a more linear behavior during operation.

公开(公告)号：US20200303371A1

公开(公告)日：2020-09-24

申请号：US16362269

申请日：2019-03-22

Applicant: Intel Corporation

Inventor： Nidhi Nidhi ,  Rahul Ramaswamy ,  Han Wui Then ,  Marko Radosavljevic ,  Johann Christian Rode ,  Paul B. Fischer ,  Walid M. Hafez

IPC: H01L27/06 ,  H01L27/01 ,  H01L21/8252

Abstract: Disclosed herein are integrated circuit structures, packages, and devices that include resistors and/or capacitors which may be provided on the same substrate/die/chip as III-N devices, e.g., III-N transistors. An integrated circuit structure, comprising a base structure comprising a III-N material, the base structure having a conductive region of a doped III-N material. The IC structure further comprises a first contact element, including a first conductive element, a dielectric element, and a second conductive element, wherein the dielectric element is between the first conductive element and the second conductive element, and wherein the first conductive element is between the conductive region and the dielectric element. The IC structure further comprises a second contact element electrically coupled to the first contact element via the conductive region.

公开(公告)号：US20200295172A1

公开(公告)日：2020-09-17

申请号：US16297837

申请日：2019-03-11

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Marko Radosavljevic ,  Han Wui Then ,  Nidhi Nidhi ,  Rahul Ramaswamy ,  Paul B. Fischer ,  Walid M. Hafez ,  Johann Christian Rode

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/08 ,  H01L29/04 ,  H01L29/66

Abstract: Disclosed herein are IC structures, packages, and device assemblies with III-N transistors that include additional materials, referred to herein as “stressor materials,” which may be selectively provided over portions of polarization materials to locally increase or decrease the strain in the polarization material. Providing a compressive stressor material may decrease the tensile stress imposed by the polarization material on the underlying portion of the III-N semiconductor material, thereby decreasing the two-dimensional electron gas (2DEG) and increasing a threshold voltage of a transistor. On the other hand, providing a tensile stressor material may increase the tensile stress imposed by the polarization material, thereby increasing the 2DEG and decreasing the threshold voltage. Providing suitable stressor materials enables easier and more accurate control of threshold voltage compared to only relying on polarization material recess.

公开(公告)号：US20200279932A1

公开(公告)日：2020-09-03

申请号：US16289824

申请日：2019-03-01

Applicant: Intel Corporation

Inventor： Nidhi Nidhi ,  Rahul Ramaswamy ,  Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Johann Christian Rode ,  Paul B. Fischer ,  Walid M. Hafez

IPC: H01L29/423 ,  H01L29/20 ,  H01L29/205 ,  H01L29/417 ,  H01L29/778 ,  H01L23/66 ,  H01L23/00 ,  H01L23/498 ,  H01L21/28 ,  H01L29/66

Abstract: Disclosed herein are IC structures, packages, and devices that include planar III-N transistors with wrap-around gates and/or one or more wrap-around source/drain (S/D) contacts. An example IC structure includes a support structure (e.g., a substrate) and a planar III-N transistor. The transistor includes a channel stack of a III-N semiconductor material and a polarization material, provided over the support structure, a pair of S/D regions provided in the channel stack, and a gate stack of a gate dielectric material and a gate electrode material provided over a portion of the channel stack between the S/D regions, where the gate stack at least partially wraps around an upper portion of the channel stack.

公开(公告)号：US20200266190A1

公开(公告)日：2020-08-20

申请号：US16279102

申请日：2019-02-19

Applicant: INTEL CORPORATION

Inventor： Marko Radosavljevic ,  Sansaptak Dasgupta ,  Han Wui Then ,  Paul B. Fischer ,  Walid M. Hafez

IPC: H01L27/06 ,  H01L29/15 ,  H01L29/20 ,  H01L29/778 ,  H01L23/66 ,  H01L23/535 ,  H01L29/66 ,  H01L21/8252

Abstract: An integrated circuit die has a layer of first semiconductor material comprising a Group III element and nitrogen and having a first bandgap. A first transistor structure on a first region of the die has: a quantum well (QW) structure that includes at least a portion of the first semiconductor material and a second semiconductor material having a second bandgap smaller than the first bandgap, a first source and a first drain in contact with the QW structure, and a gate structure in contact with the QW structure between the first source and the first drain. A second transistor structure on a second region of the die has a second source and a second drain in contact with a semiconductor body, and a second gate structure in contact with the semiconductor body between the second source and the second drain. The semiconductor body comprises a Group III element and nitrogen.

公开(公告)号：US10727339B2

公开(公告)日：2020-07-28

申请号：US15119674

申请日：2014-03-28

Applicant: Intel Corporation

Inventor： Benjamin Chu-Kung ,  Gilbert Dewey ,  Van H. Le ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Han Wui Then ,  Niloy Mukherjee ,  Sansaptak Dasgupta

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/336 ,  H01L29/66 ,  H01L29/08 ,  H01L29/739

Abstract: Vertical semiconductor devices having selectively regrown top contacts and method of fabricating vertical semiconductor devices having selectively regrown top contacts are described. For example, a semiconductor device includes a substrate having a surface. A first source/drain region is disposed on the surface of the substrate. A vertical channel region is disposed on the first source/drain region and has a first width parallel with the surface of the substrate. A second source/drain region is disposed on the vertical channel region and has a second width parallel with and substantially greater than the first width. A gate stack is disposed on and completely surrounds a portion of the vertical channel region.