公开(公告)号：US11557658B2

公开(公告)日：2023-01-17

申请号：US16649592

申请日：2017-12-27

Applicant: INTEL CORPORATION

Inventor： Gilbert Dewey ,  Sean T. Ma ,  Tahir Ghani ,  Willy Rachmady ,  Cheng-Ying Huang ,  Anand S. Murthy ,  Harold W. Kennel ,  Nicholas G. Minutillo ,  Matthew V. Metz

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

Abstract: Transistors having a plurality of channel semiconductor structures, such as fins, over a dielectric material. A source and drain are coupled to opposite ends of the structures and a gate stack intersects the plurality of structures between the source and drain. Lateral epitaxial overgrowth (LEO) may be employed to form a super-lattice of a desired periodicity from a sidewall of a fin template structure that is within a trench and extends from the dielectric material. Following LEO, the super-lattice structure may be planarized with surrounding dielectric material to expose a top of the super-lattice layers. Alternating ones of the super-lattice layers may then be selectively etched away, with the retained layers of the super-lattice then laterally separated from each other by a distance that is a function of the super-lattice periodicity. A gate dielectric and a gate electrode may be formed over the retained super-lattice layers for a channel of a transistor.

公开(公告)号：US20220375916A1

公开(公告)日：2022-11-24

申请号：US17323425

申请日：2021-05-18

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Cheng-Ying Huang ,  Ashish Agrawal ,  Gilbert W. Dewey ,  Jack T. Kavalieros ,  Abhishek A. Sharma ,  Willy Rachmady

IPC: H01L25/18 ,  H01L25/065 ,  H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: Described herein are IC devices that include multilayer memory structures bonded to compute logic using low-temperature oxide bonding to realize high-density three-dimensional (3D) dynamic random-access memory (DRAM). An example device includes a compute die, a multilayer memory structure, and an oxide bonding interface coupling the compute die to the multilayer memory structure. The oxide bonding interface includes metal interconnects and an oxide material surrounding the metal interconnects and bonding the compute die to the memory structure.

公开(公告)号：US20220352029A1

公开(公告)日：2022-11-03

申请号：US17863292

申请日：2022-07-12

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Christopher J. Jezewski ,  Willy Rachmady ,  Rishabh Mehandru ,  Gilbert Dewey ,  Anh Phan

IPC: H01L21/8234 ,  H01L29/78

Abstract: In an embodiment of the present disclosure, a device structure includes a fin structure, a gate on the fin structure, and a source and a drain on the fin structure, where the gate is between the source and the drain. The device structure further includes an insulator layer having a first insulator layer portion adjacent to a sidewall of the source, a second insulator layer portion adjacent to a sidewall of the drain, and a third insulator layer portion therebetween adjacent to a sidewall of the gate, and two or more stressor materials adjacent to the insulator layer. The stressor materials can be tensile or compressively stressed and may strain a channel under the gate.

公开(公告)号：US11469766B2

公开(公告)日：2022-10-11

申请号：US16024052

申请日：2018-06-29

Applicant: INTEL CORPORATION

Inventor： Abhishek A. Sharma ,  Ravi Pillarisetty ,  Charles Kuo ,  Willy Rachmady

IPC: H03M1/66 ,  H03M1/00 ,  H03M1/74

Abstract: Digital-to-analog converters (DACs) having a multiple-gate (multi-gate) transistor-like structure are disclosed herein. The DAC structures have a similar structure to a transistor (e.g., a MOSFET) and include source and drain regions. However, instead of employing only one gate between the source and drain regions, multiple distinct gates are employed. Each distinct gate can represent a bit for the DAC and can include different gate lengths to enable providing different current values, and thus, unique outputs. Further, N number of inputs can be applied to N number of gates employed by the DAC. The DAC structure may be configured such that the longest gate controls the LSB of the DAC and the shortest gate controls the MSB, or vice versa. In some cases, the multi-gate DAC employs high-injection velocity materials that enable compact design and routing, such as InGaAs, InP, SiGe, and Ge, to provide some examples.

公开(公告)号：US11444159B2

公开(公告)日：2022-09-13

申请号：US16612259

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Sean T. Ma ,  Gilbert Dewey ,  Willy Rachmady ,  Matthew V. Metz ,  Cheng-Ying Huang ,  Harold W. Kennel ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Tahir Ghani

IPC: H01L29/10 ,  H01L29/205 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

Abstract: An electronic device comprises a channel layer on a buffer layer on a substrate. The channel layer has a first portion and a second portion adjacent to the first portion. The first portion comprises a first semiconductor. The second portion comprises a second semiconductor that has a bandgap greater than a bandgap of the first semiconductor.

公开(公告)号：US11437405B2

公开(公告)日：2022-09-06

申请号：US16024696

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Patrick Morrow ,  Aaron Lilak ,  Willy Rachmady ,  Anh Phan ,  Ehren Mannebach ,  Hui Jae Yoo ,  Abhishek Sharma ,  Van H. Le ,  Cheng-Ying Huang

IPC: H01L29/78 ,  H01L27/12 ,  H01L21/82 ,  H01L29/786 ,  H01L21/8258

Abstract: Embodiments herein describe techniques for an integrated circuit (IC). The IC may include a first transistor, an insulator layer above the first transistor, and a second transistor above the insulator layer. The first transistor may be a p-type transistor including a channel in a substrate, a first source electrode, and a first drain electrode. A first metal contact may be coupled to the first source electrode, while a second metal contact may be coupled to the first drain electrode. The insulator layer may be next to the first metal contact, and next to the second metal contact. The second transistor may include a second source electrode, and a second drain electrode. The second source electrode may be coupled to the first metal contact, or the second drain electrode may be coupled to the second metal contact. Other embodiments may be described and/or claimed.

公开(公告)号：US11424335B2

公开(公告)日：2022-08-23

申请号：US16629555

申请日：2017-09-26

Applicant: Intel Corporation

Inventor： Sean T. Ma ,  Willy Rachmady ,  Gilbert Dewey ,  Cheng-Ying Huang ,  Dipanjan Basu

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

Abstract: Group III-V semiconductor devices having dual workfunction gate electrodes and their methods of fabrication are described. In an example, an integrated circuit structure includes a gallium arsenide layer on a substrate. A channel structure is on the gallium arsenide layer. The channel structure includes indium, gallium and arsenic. A source structure is at a first end of the channel structure and a drain structure is at a second end of the channel structure. A gate structure is over the channel structure, the gate structure having a first workfunction material laterally adjacent a second workfunction material. The second workfunction material has a different workfunction than the first workfunction material.

公开(公告)号：US20220199402A1

公开(公告)日：2022-06-23

申请号：US17133079

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Koustav Ganguly ,  Ryan Keech ,  Harold Kennel ,  Willy Rachmady ,  Ashish Agrawal ,  Glenn Glass ,  Anand Murthy ,  Jack Kavalieros

IPC: H01L21/02 ,  H01L29/16 ,  H01L27/092 ,  H01L29/78

Abstract: High-purity Ge channeled N-type transistors include a Si-based barrier material separating the channel from a Ge source and drain that is heavily doped with an N-type impurity. The barrier material may have nanometer thickness and may also be doped with N-type impurities. Because of the Si content, N-type impurities have lower diffusivity within the barrier material and can be prevented from entering high-purity Ge channel material. In addition to Si, a barrier material may also include C. With the barrier material, an N-type transistor may display higher channel mobility and reduced short-channel effects.

公开(公告)号：US11367722B2

公开(公告)日：2022-06-21

申请号：US16138356

申请日：2018-09-21

Applicant: INTEL CORPORATION

Inventor： Aaron Lilak ,  Stephen Cea ,  Gilbert Dewey ,  Willy Rachmady ,  Roza Kotlyar ,  Rishabh Mehandru ,  Sean Ma ,  Ehren Mannebach ,  Anh Phan ,  Cheng-Ying Huang

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/10 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/16

Abstract: A nanowire transistor structure has a first device region with a first body of semiconductor material having a first cross-sectional shape. A second device region has a second body with a second cross-sectional shape different from the first cross-sectional shape. The first device section is vertically above or below the second device section with the bodies extending horizontally between a source and drain. A first gate structure is wrapped around the first body and a second gate structure is wrapped around the second body. Differences in the geometries of the nanowires can be used to optimize performance in the first device section independently of the second device section.

公开(公告)号：US11342432B2

公开(公告)日：2022-05-24

申请号：US16833184

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Rishabh Mehandru ,  Cory Weber ,  Willy Rachmady ,  Varun Mishra

IPC: H01L29/423 ,  H01L21/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: Gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, and methods of fabricating gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, are described. For example, an integrated circuit structure includes an insulator fin on an insulator substrate. A vertical arrangement of horizontal semiconductor nanowires is over the insulator fin. A gate stack surrounds a channel region of the vertical arrangement of horizontal semiconductor nanowires, and the gate stack is overlying the insulator fin. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires and at first and second ends of the insulator fin.