公开(公告)号：US09947633B2

公开(公告)日：2018-04-17

申请号：US15195617

申请日：2016-06-28

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Thomas DiStefano

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/29

CPC classification number: H01L24/14 ,  H01L23/293 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L2224/13011 ,  H01L2224/13016 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/1316 ,  H01L2224/13166 ,  H01L2224/13181 ,  H01L2224/1319 ,  H01L2224/14051 ,  H01L2224/16057 ,  H01L2224/16145 ,  H01L2224/17055 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81345 ,  H01L2224/81903 ,  H01L2224/8388 ,  H01L2924/07025 ,  H01L2924/00

Abstract: Deformable conductive contacts are provided. A plurality of deformable contacts on a first substrate may be joined to a plurality of conductive pads on a second substrate during die level or wafer level assembly of microelectronics. Each deformable contact complies to a degree that is related to the amount of joining pressure between the first substrate and the second substrate. Since an individual contact can make the conductive coupling within a range of distances from a target pad, an array of the deformable contacts provides tolerance and compliance when there is some variation in height of the conductive elements on either side of the join. A flowable underfill may be provided to press the deformable contacts against opposing pads and to permanently join the surfaces at a fixed distance. The deformable contacts may include a wiping feature to clear their target pads for establishing improved metal-to-metal contact or a thermocompression bond.

公开(公告)号：US20180047704A1

公开(公告)日：2018-02-15

申请号：US15799036

申请日：2017-10-31

Applicant: Invensas Corporation

Inventor： Belgacem Haba

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L24/09 ,  H01L24/17 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/15323

Abstract: A microelectronic package includes a first microelectronic element comprising logic circuitry which is flip-chip mounted to a substrate, the substrate having terminals for connection with a circuit panel or other external component. A second microelectronic element overlies a rear surface of the first microelectronic element and has contacts electrically coupled with the substrate through electrically conductive interconnects extending through a region of the first microelectronic element. A heat spreader is thermally coupled with the rear surface of the substrate, either directly or through an additional element overlying the rear surface. Additional contacts of the second microelectronic element may be coupled with contacts of the substrate through electrically conductive structure disposed beyond an edge surface of the first microelectronic element.

公开(公告)号：US20180040587A1

公开(公告)日：2018-02-08

申请号：US15669269

申请日：2017-08-04

Applicant: Invensas Corporation

Inventor： Min Tao ,  Zhuowen Sun ,  Belgacem Haba ,  Hoki Kim ,  Wael Zohni ,  Shaowu Huang

IPC: H01L25/065 ,  H01L23/367 ,  H01L25/18 ,  H01L23/31 ,  H01L25/00 ,  H01L23/00

Abstract: Vertical memory modules enabled by fan-out redistribution layer(s) (RDLs) are provided. Memory dies may be stacked with each die having a signal pad directed to a sidewall of the die. A redistribution layer (RDL) is built on sidewalls of the stacked dies and coupled with the signal pads. The RDL may fan-out to UBM and solder balls, for example. An alternative process reconstitutes dies on a carrier with a first RDL on a front side of the dies. The dies and first RDL are encapsulated, and the modules vertically disposed for a second reconstitution on a second carrier. A second RDL is applied to exposed contacts of the vertically disposed modules and first RDLs. The vertical modules and second RDL are encapsulated in turn with a second mold material. The assembly may be singulated into individual memory modules, each with a fan-out RDL on the sidewalls of the vertically disposed dies.

公开(公告)号：US20180026011A1

公开(公告)日：2018-01-25

申请号：US15393100

申请日：2016-12-28

Applicant: Invensas Corporation

Inventor： Min Tao ,  Hoki Kim ,  Ashok S. Prabhu ,  Zhuowen Sun ,  Wael Zohni ,  Belgacem Haba

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L21/52

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/52 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/5283 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/09 ,  H01L24/46 ,  H01L24/49 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/071 ,  H01L25/105 ,  H01L25/112 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/19107

Abstract: Package-on-package (“PoP”) devices with same level wafer-level packaged (“WLP”) components and methods therefor are disclosed. In a PoP device, a first integrated circuit die is surface mount coupled to an upper surface of a package substrate. Conductive lines are coupled to the upper surface of the package substrate in a fan-out region. The first conductive lines extend away from the upper surface of the package substrate. A molding layer is formed over the upper surface of the package substrate, around sidewall surfaces of the first integrated circuit die, and around bases and shafts of the conductive lines. WLP microelectronic components are located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines.

公开(公告)号：US09856135B2

公开(公告)日：2018-01-02

申请号：US15380391

申请日：2016-12-15

Applicant: Invensas Corporation

Inventor： Chang Myung Ryu ,  Kimitaka Endo ,  Belgacem Haba ,  Yoichi Kubota

IPC: H01L21/48 ,  B81B7/00 ,  H01L23/498 ,  B81C1/00 ,  C25D7/00 ,  H01L21/768 ,  H01L23/00

CPC classification number: B81B7/0006 ,  B81C1/00539 ,  C25D7/00 ,  H01L21/4846 ,  H01L21/768 ,  H01L23/498 ,  H01L24/19 ,  H01L24/24 ,  H01L2224/244 ,  H01L2924/0002 ,  H01L2924/12042 ,  H01L2924/00

Abstract: A microelectronic interconnect element can include a plurality of first metal lines and a plurality of second metal lines interleaved with the first metal lines. Each of the first and second metal lines has a surface extending within the same reference plane. The first metal lines have surfaces above the reference plane and remote therefrom and the second metal lines have surfaces below the reference plane and remote therefrom. A dielectric layer can separate a metal line of the first metal lines from an adjacent metal line of the second metal lines.

公开(公告)号：US09852994B2

公开(公告)日：2017-12-26

申请号：US15354061

申请日：2016-11-17

Applicant: Invensas Corporation

Inventor： Belgacem Haba

IPC: H05K7/02 ,  H01L23/538 ,  H01L21/48

CPC classification number: H01L23/5381 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/81192 ,  H01L2924/15159 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15313

Abstract: Embedded vialess bridges are provided. In an implementation, discrete pieces containing numerous conduction lines or wires in a 3-dimensional bridge piece are embedded where needed in a main substrate to provide dense arrays of signal, power, and electrical ground wires below the surface of the main substrate. Vertical conductive risers to reach the surface plane of the main substrate are also included in the discrete piece, for connecting to dies on the surface of the substrate and thereby interconnecting the dies to each other through the dense array of wires in the discrete piece. The discrete piece to be embedded may have parallel planes of conductors at regular intervals within itself, and thus may present a working surface homogeneously covered with the ends of vertical conductors available to connect surface components to each other and to ground and power at many places along the embedded piece.

公开(公告)号：US09832887B2

公开(公告)日：2017-11-28

申请号：US13961217

申请日：2013-08-07

Applicant: Invensas Corporation

Inventor： Liang Wang ,  Ilyas Mohammed ,  Belgacem Haba

IPC: H05K3/40 ,  H05K3/42 ,  H01L21/48 ,  H01L23/498 ,  H05K1/02 ,  H05K1/11

CPC classification number: H05K3/42 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49827 ,  H01L2224/16225 ,  H05K1/0296 ,  H05K1/11 ,  Y10T29/49204

Abstract: Components and methods of making the same are disclosed herein. In one embodiment, a method of forming a component comprises forming metal anchoring elements at a first surface of a support element having first and second oppositely facing surfaces, the support element having a thickness extending in a first direction between the first and second surfaces, wherein each anchoring element has a downwardly facing overhang surface; and then forming posts having first ends proximate the first surface and second ends disposed above the respective first ends and above the first surface, wherein a laterally extending portion of each post contacts at least a first area of the overhang surface of the respective anchoring element and extends downwardly therefrom, and the overhang surface of the anchoring element resists axial and shear forces applied to the posts at positions above the anchoring elements.

公开(公告)号：US09728495B2

公开(公告)日：2017-08-08

申请号：US14775119

申请日：2014-03-10

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Richard Dewitt Crisp ,  Wael Zohni

IPC: H01L23/02 ,  H01L23/498 ,  H01L25/065 ,  H01L23/538 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  H01L25/10 ,  H01L23/00

CPC classification number: H01L23/49811 ,  G11C5/025 ,  G11C5/04 ,  G11C5/063 ,  H01L23/49816 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A microelectronic package (10) can include lower and upper package faces (11, 12), lower terminals (25) at the lower package face, upper terminals (45) at the upper package face, first and second microelectronic elements (30) each having memory storage array function, and conductive interconnects (15) each electrically connecting at least one lower terminal with at least one upper terminal. The conductive interconnects (15) can include first conductive interconnects (15a) configured to carry address in formation, signal assignments of a first set (70a) of the first interconnects having (180) rotational symmetry about a theoretical rotational axis (29) with signal assignments of a second set (70b) of first interconnects. The conductive interconnects (15) can also include second conductive interconnects (15b) configured to carry data information, the position of each second conductive interconnect having (180) rotational symmetry about the rotational axis (29) with a position of a corresponding no-connect conductive interconnect (15d).

公开(公告)号：US20170179081A1

公开(公告)日：2017-06-22

申请号：US15358380

申请日：2016-11-22

Applicant: Invensas Corporation

Inventor： Javier A. Delacruz ,  Belgacem Haba ,  Tu Tam Vu ,  Rajesh Katkar

IPC: H01L25/065 ,  H01L23/495

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49555 ,  H01L23/49575 ,  H01L23/49838 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/49051 ,  H01L2224/4909 ,  H01L2224/49113 ,  H01L2224/49173 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/06 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: Stacked microelectronic packages comprise microelectronic elements each having a contact-bearing front surface and edge surfaces extending away therefrom, and a dielectric encapsulation region contacting an edge surface. The encapsulation defines first and second major surfaces of the package and a remote surface between the major surfaces. Package contacts at the remote surface include a first set of contacts at positions closer to the first major surface than a second set of contacts, which instead are at positions closer to the second major surface. The packages are configured such that major surfaces of each package can be oriented in a nonparallel direction with the major surface of a substrate, the package contacts electrically coupled to corresponding contacts at the substrate surface. The package stacking and orientation can provide increased packing density.

公开(公告)号：US20170170121A1

公开(公告)日：2017-06-15

申请号：US15354061

申请日：2016-11-17

Applicant: Invensas Corporation

Inventor： Belgacem Haba

IPC: H01L23/538 ,  H01L21/48

CPC classification number: H01L23/5381 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/81192 ,  H01L2924/15159 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15313

Abstract: Embedded vialess bridges are provided. In an implementation, discrete pieces containing numerous conduction lines or wires in a 3-dimensional bridge piece are embedded where needed in a main substrate to provide dense arrays of signal, power, and electrical ground wires below the surface of the main substrate. Vertical conductive risers to reach the surface plane of the main substrate are also included in the discrete piece, for connecting to dies on the surface of the substrate and thereby interconnecting the dies to each other through the dense array of wires in the discrete piece. The discrete piece to be embedded may have parallel planes of conductors at regular intervals within itself, and thus may present a working surface homogeneously covered with the ends of vertical conductors available to connect surface components to each other and to ground and power at many places along the embedded piece.