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    SINGULATING HYBRID INTEGRATED PHOTONIC CHIPS
    26.
    发明申请
    SINGULATING HYBRID INTEGRATED PHOTONIC CHIPS 有权
    混合混合光电池

    公开(公告)号：US20150108506A1

    公开(公告)日：2015-04-23

    申请号：US14059288

    申请日：2013-10-21

    Applicant: Oracle International Corporation

    Inventor： Chaoqi Zhang ,  Hiren D. Thacker ,  Ashok V. Krishnamoorthy

    IPC: H01L21/82 ,  H01L31/12 ,  H01L31/18

    CPC classification number: H01L31/12 ,  H01L21/78 ,  H01L31/18

    Abstract: During a fabrication technique, trenches are defined partially through the thickness of a substrate. Then, photonic integrated circuits are coupled to the substrate. These photonic integrated circuits may be in a diving-board configuration, so that they at least partially overlap the trenches. While this may preclude the use of existing dicing techniques, individual hybrid integrated photonic chips (which each include a portion of the substrate and at least one of the photonic integrated circuits) may be singulated from the substrate by: coupling a carrier to a front surface of the substrate; thinning the substrate from a back surface until the partial trenches are reached (for example, by grinding the substrate); attaching a support mechanism (such as tape) to the back surface of the substrate; removing the carrier; and then removing the support mechanism.

    Abstract translation: 在制造技术期间，通过衬底的厚度部分限定沟槽。 然后，光子集成电路耦合到衬底。 这些光子集成电路可以处于潜水板配置中，使得它们至少部分地与沟槽重叠。 虽然这可能排除了使用现有的切割技术，但是可以通过以下方式将单个混合集成光子芯片（其中每个包括基板的一部分和至少一个光子集成电路）分离成：将载体耦合到前表面 的基底; 从背面稀释基板直到达到部分沟槽（例如，通过研磨基板）; 将支撑机构（例如胶带）附接到基板的背面; 移除载体; 然后卸下支撑机构。

    Stackable photonic interconnect module
    28.
    发明授权
    Stackable photonic interconnect module 有权
    可堆叠光子互连模块

    公开(公告)号：US08998509B2

    公开(公告)日：2015-04-07

    申请号：US13831519

    申请日：2013-03-14

    Applicant: Oracle International Corporation

    Inventor： Hiren D. Thacker ,  Xuezhe Zheng ,  Ashok V. Krishnamoorthy ,  Gary L. Gilbert

    IPC: G02B6/36 ,  G02B6/42 ,  H04B10/27 ,  G02B6/43

    CPC classification number: G02B6/4284 ,  G02B6/4279 ,  G02B6/43 ,  H04B10/27 ,  H04B10/801

    Abstract: An interconnect module for communicating electrical signals and optical signals is described. In particular, an integrated circuit in the interconnect module receives and transmits the electrical signals with other components in a system that includes the interconnect module via an electrical connector. In addition, the integrated circuit receives and transmits electrical signals to a hybrid silicon-photonic bridge chip that performs electrical-to-optical and optical-to-electrical conversion. In turn, this bridge chip receives and transmits optical signals via an optical fiber. The interconnect module can be remateably connected to a backplane in the system, and can be arranged in a stacked configuration with other instances of the interconnect module. In these ways, the interconnect module facilitates dense, modular or scalable, and compact electrical and optical communication in the system.

    Abstract translation: 描述了用于传送电信号和光信号的互连模块。 特别地，互连模块中的集成电路经由电连接器接收并传输包括互连模块的系统中的其它部件的电信号。 此外，集成电路接收并发送电信号到执行电 - 光和光 - 电转换的混合硅 - 光子桥芯片。 反过来，该桥芯片通过光纤接收和发送光信号。 互连模块可以可重新连接到系统中的背板，并且可以以互连模块的其他实例布置成堆叠配置。 以这些方式，互连模块便于在系统中进行密集，模块化或可缩放的电气和光通信。

    CHIP PACKAGE FOR HIGH-COUNT CHIP STACKS
    30.
    发明申请
    CHIP PACKAGE FOR HIGH-COUNT CHIP STACKS 有权
    大批芯片堆栈的芯片包装

    公开(公告)号：US20140225273A1

    公开(公告)日：2014-08-14

    申请号：US13764331

    申请日：2013-02-11

    Applicant: ORACLE INTERNATIONAL CORPORATION

    Inventor： Hiren D. Thacker ,  John E. Cunningham ,  Ashok Krishnamoorthy

    IPC: H01L23/538 ,  H01L21/02

    CPC classification number: H01L23/5384 ,  H01L23/13 ,  H01L23/145 ,  H01L23/147 ,  H01L23/15 ,  H01L23/481 ,  H01L25/0652 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/16225 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A chip package is described. This chip package includes a substrate having a side at an angle relative to the top and bottom surfaces of the substrate that is between that of a direction parallel to the top and bottom surfaces and that of a direction perpendicular to the top and bottom surfaces (i.e., between 0° and 90°). This side may be configured to couple to a stack of semiconductor dies in which the semiconductor dies are offset from each other in a direction parallel to the top and bottom surfaces so that one side of the stack defines a stepped terrace. For example, the side may include electrical pads. These electrical pads may be coupled to electrical pads on the top surface by through-substrate vias (TSVs) in the substrate. Moreover, the electrical pads on the top surface may be configured to couple to an integrated circuit.

    Abstract translation: 描述了芯片封装。 该芯片封装包括具有相对于基板的顶表面和底表面成一定角度的侧面的基板，该基板位于平行于顶部和底部表面的方向与垂直于顶部和底部表面的方向（即 在0°和90°之间）。 这一侧可以被配置成耦合到半导体管芯的堆叠，其中半导体管芯在平行于顶部和底部表面的方向上彼此偏移，使得堆叠的一侧限定阶梯式台阶。 例如，侧面可以包括电垫。 这些电焊盘可以通过衬底中的通孔衬底（TSV）耦合到顶表面上的电焊盘。 此外，顶表面上的电焊盘可以被配置成耦合到集成电路。

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