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    Back-side etching and cleaving of substrates
    21.
    发明授权
    Back-side etching and cleaving of substrates 有权

    公开(公告)号：US10514502B2

    公开(公告)日：2019-12-24

    申请号：US15223509

    申请日：2016-07-29

    Applicant: Oracle International Corporation

    Inventor： Jin-Hyoung Lee ,  Ivan Shubin ,  Xuezhe Zheng ,  Ashok V. Krishnamoorthy

    IPC: G02B6/13 ,  G02B6/122 ,  G02B6/136 ,  H01L21/3065 ,  H01L21/78

    Abstract: A fabrication technique for cleaving a substrate in an integrated circuit is described. During this fabrication technique, a trench is defined on a back side of a substrate. For example, the trench may be defined using photoresist and/or a mask pattern on the back side of the substrate. The trench may extend from the back side to a depth less than a thickness of the substrate. Moreover, a buried-oxide layer and a semiconductor layer may be disposed on a front side of the substrate. In particular, the substrate may be included in a silicon-on-insulator technology. By applying a force proximate to the trench, the substrate may be cleaved to define a surface, such as an optical facet. This surface may have high optical quality and may extend across the substrate, the buried-oxide layer and the semiconductor layer.

    HYBRID-INTEGRATED MULTI-CHIP MODULE
    23.
    发明申请
    HYBRID-INTEGRATED MULTI-CHIP MODULE 有权

    公开(公告)号：US20170199328A1

    公开(公告)日：2017-07-13

    申请号：US14994976

    申请日：2016-01-13

    Applicant: Oracle International Corporation

    Inventor： Ivan Shubin ,  Xuezhe Zheng ,  Jin Hyoung Lee ,  Ashok V. Krishnamoorthy

    IPC: G02B6/122 ,  H01S5/022 ,  G02B6/42

    CPC classification number: G02B6/122 ,  G02B6/1228 ,  G02B6/4231 ,  G02B6/4274 ,  G02B6/428 ,  G02B2006/12121 ,  G02B2006/12147 ,  H01S5/0228

    Abstract: A multi-chip module (MCM) is described. This MCM includes a driver integrated circuit that includes electrical circuits, a photonic chip, an interposer, and an optical gain chip. The photonic chip may be implemented using a silicon-on-insulator technology, and may include an optical waveguide that conveys an optical signal and traces that are electrically coupled to the driver integrated circuit. Moreover, the interposer may be electrically coupled to the traces. Furthermore, the optical gain chip may include a III/V compound semiconductor (and, more generally, a semiconductor other than silicon), and may include a second optical waveguide that conveys the optical signal and that is vertically aligned with the optical waveguide relative to a top surface of the interposer. Additionally, the optical gain chip may be electrically coupled to the interposer.

    Hybrid integration of edge-coupled chips
    24.
    发明授权
    Hybrid integration of edge-coupled chips 有权

    公开(公告)号：US09618709B2

    公开(公告)日：2017-04-11

    申请号：US14060136

    申请日：2013-10-22

    Applicant: Oracle International Corporation

    Inventor： Xuezhe Zheng ,  Ivan Shubin ,  Ying Luo ,  Guoliang Li ,  Ashok V. Krishnamoorthy

    IPC: G02B6/42 ,  G02B6/14

    CPC classification number: G02B6/4224 ,  G02B6/00 ,  G02B6/14

    Abstract: A technique for fabricating a hybrid optical source is described. During this fabrication technique, a III-V compound-semiconductor active gain medium is integrated with a silicon-on-insulator (SOI) chip (or wafer) using edge coupling to form a co-planar hybrid optical source. Using a backside etch-assisted cleaving technique, and a temporary transparent substrate with alignment markers, a III-V compound-semiconductor chip with proper edge polish and coating can be integrated with a processed SOI chip (or wafer) with accurate alignment. This fabrication technique may significantly reduce the alignment complexity when fabricating the hybrid optical source, and may enable wafer-scale integration.

    Self-assembled vertically aligned multi-chip module
    25.
    发明授权
    Self-assembled vertically aligned multi-chip module 有权
    自组装垂直排列的多芯片模块

    公开(公告)号：US09519105B1

    公开(公告)日：2016-12-13

    申请号：US15188403

    申请日：2016-06-21

    Applicant: Oracle International Corporation

    Inventor： Ivan Shubin ,  Xuezhe Zheng ,  Jin Hyoung Lee ,  Kannan Raj ,  Ashok V. Krishnamoorthy

    IPC: G02B6/26 ,  G02B6/13 ,  G02B6/42 ,  G02B6/12 ,  H01S5/30 ,  H01L33/58 ,  G02B6/43

    CPC classification number: G02B6/13 ,  G02B6/12 ,  G02B6/4228 ,  G02B6/4239 ,  G02B6/4257 ,  G02B6/43 ,  G02B2006/12061 ,  H01L33/58 ,  H01S5/3013

    Abstract: A multi-chip module (MCM) is described. This MCM includes two substrates that are passively self-assembled on another substrate using hydrophilic and hydrophobic materials on facing surfaces of the substrates and liquid surface tension as the restoring force. In particular, regions with a hydrophilic material on the two substrates overlap regions with the hydrophilic material on the other substrate. These regions on the other substrate may be surrounded by a region with a hydrophobic material. In addition, spacers on a surface of at least one of the two substrates may align optical waveguides disposed on the two substrates, so that the optical waveguides are coplanar. This fabrication technique may allow low-loss hybrid optical sources to be fabricated by edge coupling the two substrates. For example, a first of the two substrates may be a III/V compound semiconductor and a second of the two substrates may be a silicon-on-insulator photonic chip.

    Abstract translation: 描述了多芯片模块（MCM）。 该MCM包括两个衬底，其被动地自组装在另一衬底上，使用在衬底的相对表面上的亲水和疏水材料和作为恢复力的液体表面张力。 特别地，在两个基底上具有亲水性材料的区域与另一个基底上的亲水材料重叠区域。 另一个衬底上的这些区域可以被具有疏水性材料的区域包围。 此外，两个基板中的至少一个的表面上的间隔物可以对准设置在两个基板上的光波导，使得光波导是共面的。 这种制造技术可以允许通过边缘耦合两个基板来制造低损耗混合光源。 例如，两个基板中的第一个可以是III / V化合物半导体，并且两个基板中的第二个可以是绝缘体上硅光子芯片。

    Back-side etching and cleaving of substrates
    26.
    发明授权
    Back-side etching and cleaving of substrates 有权
    背面蚀刻和基板裂开

    公开(公告)号：US09488777B2

    公开(公告)日：2016-11-08

    申请号：US14024227

    申请日：2013-09-11

    Applicant: Oracle International Corporation

    Inventor： Jin-Hyoung Lee ,  Ivan Shubin ,  Xuezhe Zheng ,  Ashok V. Krishnamoorthy

    IPC: G02B6/122 ,  G02B6/13

    CPC classification number: G02B6/13 ,  G02B6/122 ,  G02B6/136 ,  H01L21/3065 ,  H01L21/7806

    Abstract: A fabrication technique for cleaving a substrate in an integrated circuit is described. During this fabrication technique, a trench is defined on a back side of a substrate. For example, the trench may be defined using photoresist and/or a mask pattern on the back side of the substrate. The trench may extend from the back side to a depth less than a thickness of the substrate. Moreover, a buried-oxide layer and a semiconductor layer may be disposed on a front side of the substrate. In particular, the substrate may be included in a silicon-on-insulator technology. By applying a force proximate to the trench, the substrate may be cleaved to define a surface, such as an optical facet. This surface may have high optical quality and may extend across the substrate, the buried-oxide layer and the semiconductor layer.

    Abstract translation: 描述了用于在集成电路中切割衬底的制造技术。 在该制造技术期间，沟槽被限定在衬底的背面。 例如，可以使用光致抗蚀剂和/或在衬底的背面上的掩模图案来限定沟槽。 沟槽可以从背侧延伸到小于衬底的厚度的深度。 此外，可以在衬底的前侧上设置掩埋氧化物层和半导体层。 特别地，衬底可以包括在绝缘体上硅技术中。 通过施加靠近沟槽的力，衬底可以被切割以限定诸如光学面的表面。 该表面可以具有高的光学质量并且可以延伸穿过衬底，掩埋氧化物层和半导体层。

    Single shot correction of resonant optical components
    27.
    发明授权
    Single shot correction of resonant optical components 有权
    谐振光学元件的单次校正

    公开(公告)号：US09465169B2

    公开(公告)日：2016-10-11

    申请号：US14625023

    申请日：2015-02-18

    Applicant: Oracle International Corporation

    Inventor： Stevan S. Djordjevic ,  Shiyun Lin ,  Ivan Shubin ,  Xuezhe Zheng ,  John E. Cunningham ,  Ashok V. Krishnamoorthy

    IPC: G02B6/12 ,  G02B6/293 ,  G02B6/13 ,  G02F1/225 ,  B01J37/34 ,  B01J37/12

    CPC classification number: G02B6/29395 ,  G02B6/13 ,  G02B6/2934 ,  G02F1/2257

    Abstract: An optical device is described. This optical device includes optical components having resonance wavelengths that match target values with a predefined accuracy (such as 0.1 nm) and with a predefined time stability (such as permanent or an infinite time stability) without thermal tuning and/or electronic tuning. The stable, accurate resonance wavelengths may be achieved using a wafer-scale, single (sub-second) shot trimming technique that permanently corrects the phase errors induced by material variations and fabrication inaccuracies in the optical components (and, more generally, resonant silicon-photonic optical components). In particular, the trimming technique may use photolithographic exposure of the optical components on the wafer in parallel, with time-modulation for each individual optical component based on active-element control. Note that the physical mechanism in the trimming technique may involve superficial room-temperature oxidation of the silicon surface, which is induced by deep-ultraviolet radiation in the presence of oxygen.

    Abstract translation: 描述光学装置。 该光学装置包括具有与预定精度（例如0.1nm）匹配的目标值的谐振波长的光学部件，并且具有预定的时间稳定性（例如永久或无限时间稳定性），而不需要热调谐和/或电子调谐。 稳定，准确的共振波长可以使用晶片级单次（亚秒级）拍摄微调技术来实现，该技术永久地校正由光学部件中的材料变化和制造不精确性引起的相位误差（以及更一般地，谐振硅 - 光子学组件）。 特别地，修剪技术可以使用基于有源元件控制的每个单独光学部件的时间调制来并行地对晶片上的光学部件进行光刻曝光。 注意，修整技术中的物理机制可能涉及在氧存在下由深紫外线辐射诱导的硅表面的室温室温氧化。

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