公开(公告)号：US20170083451A1

公开(公告)日：2017-03-23

申请号：US14930666

申请日：2015-11-03

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kok-Yong Tan

IPC: G06F12/10 ,  G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/1041 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7203 ,  G06F2212/7207

Abstract: A buffer memory management method, a memory control circuit unit and a memory storage device are provided. The buffer memory management method includes allocating a mapping table zone having a first zone and a second zone in the buffer memory, and temporarily storing a plurality of logical address-physical address mapping tables into the first zone and the second zone, and receiving a first write command which indicates writing first data into a first logical address. A first logical address-physical address mapping table to which the first logical address belongs is temporarily stored into a first buffer unit in the second zone. The method also includes updating the first logical address-physical address mapping table, moving the updated first logical address-physical address mapping table into a second buffer unit in the first zone, and marking the second buffer unit as a dirty status.

公开(公告)号：US20170010961A1

公开(公告)日：2017-01-12

申请号：US14824092

申请日：2015-08-12

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kok-Yong Tan

IPC: G06F12/02 ,  G11C16/16

CPC classification number: G06F12/0246 ,  G06F2212/1036 ,  G06F2212/7201 ,  G06F2212/7205 ,  G06F2212/7207 ,  G06F2212/7211 ,  G11C16/00 ,  G11C16/16 ,  G11C16/349 ,  G11C16/3495

Abstract: A wear leveling method for a rewritable non-volatile memory module is provided. The method includes: recording a timestamp for each of physical erasing units storing valid data according to a programming sequence of the physical erasing units storing valid data among the physical erasing units, and recording an erase count for each of physical erasing units. The method also includes: selecting a first physical erasing unit from the physical erasing units storing valid data according to the timestamps, selecting a second physical erasing unit from physical erasing units not storing valid data among the physical erasing units according to the erase counts, and writing valid data of the first physical erasing unit into the second physical erasing unit, and marking the first physical erasing unit as a physical erasing unit not storing valid data.

Abstract translation: 提供了一种用于可重写非易失性存储器模块的磨损均衡方法。 该方法包括：根据在物理擦除单元之间存储有效数据的物理擦除单元的编程序列，记录存储有效数据的每个物理擦除单元的时间戳，并记录每个物理擦除单元的擦除计数。 该方法还包括：从根据时间戳存储有效数据的物理擦除单元中选择第一物理擦除单元，根据擦除计数从物理擦除单元中存储有效数据的物理擦除单元选择第二物理擦除单元;以及 将第一物理擦除单元的有效数据写入第二物理擦除单元，以及将第一物理擦除单元标记为不存储有效数据的物理擦除单元。

公开(公告)号：US20160364148A1

公开(公告)日：2016-12-15

申请号：US14825178

申请日：2015-08-13

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kok-Yong Tan

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0611 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688

Abstract: A method for accessing a buffer memory in a memory storage device is provided, wherein the buffer memory, which has a plurality of write buffer units, is equipped in the memory storage device having a rewritable non-volatile memory module. The method includes: receiving a write data from a host system and determining whether the number of used write buffer unit is smaller than a predefined value or not. The method also includes: if the number of the used write buffer unit is not smaller than the predefined value, temporarily storing the write data into one of the write buffer unit which is not being used and transmitting a confirmation message corresponding to the write data to the host system after a predefined time interval. Therefore, the method can reduce the latency of write operations of the host system.

Abstract translation: 提供了一种用于访问存储器存储装置中的缓冲存储器的方法，其中具有多个写缓冲器单元的缓冲存储器装备在具有可重写非易失性存储器模块的存储器存储装置中。 该方法包括：从主机系统接收写入数据，并确定所使用的写入缓冲器单元的数量是否小于预定义值。 该方法还包括：如果所使用的写入缓冲器单元的数量不小于预定值，则将写入数据临时存储到未被使用的写入缓冲器单元之一并将与写入数据相对应的确认消息发送到 主机系统经过预定义的时间间隔。 因此，该方法可以减少主机系统的写入操作的等待时间。

公开(公告)号：US11907059B2

公开(公告)日：2024-02-20

申请号：US17715050

申请日：2022-04-07

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kok-Yong Tan

IPC: G06F11/07 ,  G06F1/30 ,  G06F3/06

CPC classification number: G06F11/0793 ,  G06F1/30 ,  G06F3/065 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/0689 ,  G06F11/073

Abstract: An abnormal power loss recovery method, a memory control circuit unit, and a memory storage device are provided. The method is configured for a memory storage device including a rewritable non-volatile memory module having a plurality of super-physical units. The super-physical units include at least two physical erasing units, and each of the physical erasing units belongs to a different operation unit and includes a plurality of physical programming units. The method includes: reading data stored in a first super-physical unit without a corresponding RAID ECC code when a memory storage device is powered on again and detected as an abnormal power loss to obtain first data, and the first super-physical unit is a last super-physical unit to which data is written before the abnormal power loss occurs; and copying the first data to a second super-physical unit.

公开(公告)号：US11221946B2

公开(公告)日：2022-01-11

申请号：US16835268

申请日：2020-03-30

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kok-Yong Tan

IPC: G06F12/02 ,  G06F12/06 ,  G06F3/06 ,  G06F12/0882 ,  G06F11/30 ,  G11C16/14 ,  G06F9/30

Abstract: A data arrangement method, a memory storage device and a memory control circuit unit are provided. The data arrangement method includes: receiving a command from a host, and the command includes a data range; calculating a data disarranged degree according to a logical estimated value of a plurality of logical block addresses of the data range and a physical estimated value of a plurality of physical erasing units mapped to the plurality of logical block addresses of the data range; and determining whether to perform a data arrangement operation according to the data disarranged degree and a threshold to move data in the plurality of physical erasing units according to the plurality of logical block addresses.

公开(公告)号：US10884652B2

公开(公告)日：2021-01-05

申请号：US16004443

申请日：2018-06-11

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kok-Yong Tan

IPC: G06F3/06 ,  G06F12/02

Abstract: A trim command recording method, a memory control circuit unit and a memory storage device are provided. The method includes: receiving a write command from a host system; writing a data corresponding to the write command to a first physical programming unit of a first physical erasing unit in the plurality of physical erasing units; and when receiving a trim command from the host system, writing a trim command record corresponding to the trim command into a second physical programming unit of the first physical erasing unit.

公开(公告)号：US10564862B2

公开(公告)日：2020-02-18

申请号：US15989197

申请日：2018-05-25

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kok-Yong Tan

IPC: G06F3/06 ,  G06F12/1009

Abstract: A wear leveling method for a rewritable non-volatile memory module, a memory control circuit unit, and a memory storage apparatus are provided. The rewritable non-volatile memory module includes a plurality of physical erasing units. The method includes: recording an operation value of each of the physical erasing units; recording a usage situation value of each of the physical erasing units; and selecting a first physical erasing unit and a second physical erasing unit from the physical erasing units according to the operation values of the physical erasing units and the usage situation values of the physical erasing units and copying valid data stored in the first physical erasing unit to the second physical erasing unit.

公开(公告)号：US20190317673A1

公开(公告)日：2019-10-17

申请号：US15989197

申请日：2018-05-25

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kok-Yong Tan

IPC: G06F3/06 ,  G06F12/1009

Abstract: A wear leveling method for a rewritable non-volatile memory module, a memory control circuit unit, and a memory storage apparatus are provided. The rewritable non-volatile memory module includes a plurality of physical erasing units. The method includes: recording an operation value of each of the physical erasing units; recording a usage situation value of each of the physical erasing units; and selecting a first physical erasing unit and a second physical erasing unit from the physical erasing units according to the operation values of the physical erasing units and the usage situation values of the physical erasing units and copying valid data stored in the first physical erasing unit to the second physical erasing unit.

公开(公告)号：US10191659B2

公开(公告)日：2019-01-29

申请号：US14997576

申请日：2016-01-18

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kok-Yong Tan

IPC: G06F3/06

Abstract: A data access method for a memory storage device is provided. The memory storage device includes a rewritable non-volatile memory module and a buffer memory. The method includes: receiving at least one operation command including at least one read command; and counting an amount of accumulative data of the at least one read command, and if the amount of accumulative data reaches a data threshold, writing the data in the buffer memory into the rewritable non-volatile memory module.

公开(公告)号：US09946478B2

公开(公告)日：2018-04-17

申请号：US15145814

申请日：2016-05-04

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kok-Yong Tan

IPC: G06F3/06 ,  G11C16/34

CPC classification number: G06F3/0619 ,  G06F3/065 ,  G06F3/0688 ,  G11C16/3427 ,  G11C16/3431

Abstract: A memory managing method, a memory control circuit unit and a memory storage apparatus are provided. The method includes: setting a read-disturb threshold for each of a plurality of physical erasing units; adjusting the read-disturb threshold of a first physical erasing unit according to state information of a rewritable non-volatile memory module; and performing a read-disturb prevention operation according to the read-disturb threshold of the first physical erasing unit.