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公开(公告)号：US10130280B2
公开(公告)日：2018-11-20
申请号：US14711042
申请日：2015-05-13
Applicant: Raytheon Company
Inventor： Matthew D. Chambers , John L. Vampola , Micky Harris
Abstract: A system including a detector array configured to receive electromagnetic (EM) radiation from a target object, the detector array having one or more detectors is disclosed. The system also includes a readout integrated circuit and one or more processors. The readout integrated circuit has a circuit comprising a number of detector boundary selection components, each one of the number of detector boundary selection components configured to select or adjust a detector boundary from least one of a sub-column boundary or an adjustable boundary.
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公开(公告)号：US09774802B2
公开(公告)日：2017-09-26
申请号：US14536733
申请日：2014-11-10
Applicant: RAYTHEON COMPANY
Inventor： Bryan W. Kean , John L. Vampola
IPC: H04N5/355 , H04N5/3745
CPC classification number: H04N5/3559 , H04N5/3745 , H04N5/37452
Abstract: According to one aspect, embodiments herein provide a unit cell comprising a photodiode, a MOSCap having an input node coupled to the photodiode, a reset switch selectively coupled between the MOSCap and a reset voltage, and a transistor coupled to the input node of the MOSCap, wherein, in a first mode of operation of the unit cell, the reset switch is configured in an open state and charge generated by light incident on the photodiode accumulates at the input node of the MOSCap in response to voltage at the input node being less than a threshold voltage, and wherein, in a second mode of operation of the unit cell, the reset switch is configured in the open state and the charge generated by the light incident on the photodiode accumulates on the MOSCap in response to the voltage at the input node being greater than the threshold voltage.
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23.发明申请METHOD AND SYSTEM FOR MANAGING DEFECTS IN FOCAL PLANE ARRAYS USING REDUNDANT COMPONENTS 审中-公开管理使用冗余组件的正面平面阵列缺陷的方法和系统公开(公告)号：US20150288907A1
公开(公告)日：2015-10-08
申请号：US14244032
申请日：2014-04-03
Applicant: RAYTHEON COMPANY
Inventor： John L. Vampola , Micky R. Harris , Bryan W. Kean , Steven E. Botts
IPC: H04N5/3745 , H04N5/376 , H01L27/146
CPC classification number: H04N5/3745 , H01L27/14643 , H04N5/367 , H04N5/3765 , H04N5/378 , H04N17/002
Abstract: A focal plane array having: an imaging array section, comprising: an array of electromagnetic radiation detectors; and an address section providing outputs from selectively enabled detectors. The imaging array section comprises a plurality of circuit blocks, each one of the circuit blocks having a primary circuit and a redundant circuit. Test circuitry is for provided for supplying test signals to test each one of the primary circuits and determining whether a response from the test signals is proper or improper and for storing in the test circuitry in response to such determining select signals associated with each one of the tested circuit blocks. An array controller is provided for, during a subsequent normal operating mode, providing timing pulses to the address section wherein the address section selectively enables the detectors using either the primary or redundant circuits in the plurality of circuit blocks selectively in accordance with the stored select signals.
Abstract translation: 1.一种焦平面阵列，具有：成像阵列部，包括：电磁辐射检测器阵列; 以及提供来自选择性启用的检测器的输出的地址部分。 成像阵列部分包括多个电路块，每个电路块具有主电路和冗余电路。 测试电路用于提供测试信号以测试主电路中的每一个，并且确定来自测试信号的响应是否适当或不正确，并且响应于这样的确定选择信号而存储在测试电路中 测试电路块。 提供阵列控制器，用于在随后的正常操作模式期间向地址部分提供定时脉冲，其中地址部分根据存储的选择信号有选择地使能多个电路块中的主电路或冗余电路的检测器 。
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24.发明申请Electro-Optical (EO)/Infrared (IR) Staring Focal Planes With High Rate Region of Interest Processing And Event Driven Forensic Look-Back Capability 有权电光（EO）/红外（IR）凝视焦平面与高利率感兴趣区域处理和事件驱动的法医回溯能力公开(公告)号：US20150163401A1
公开(公告)日：2015-06-11
申请号：US14099119
申请日：2013-12-06
Applicant: Raytheon Company
Inventor： Steven E. Botts , Micky R. Harris , John L. Vampola , Michael McLaughlin
CPC classification number: H04N5/23229 , G06K9/46 , G06K2009/4666 , H04N5/332 , H04N5/341 , H04N5/369 , H04N5/37452
Abstract: A focal plane array having: a plurality of detectors; a plurality of unit cell sections, each section being fed by charge produced by corresponding detector for producing a sequence of frames; and a plurality of sets of storage sections, each section being coupled to a corresponding one of the unit cells. Each set of storage sections includes a plurality of storage units for sequentially storing the frames. A region of interest selector section examines the frames of the plurality of unit calls, to detect at least one of the frames having a predetermined characteristic. A processor: (i) identifies a sub-set of the plurality of unit cells proximate the detected unit cells having the predetermined characteristic to establish a region of interest; and (ii) sequentially reads the plurality of storage units in the storage sections coupled to the sub-set of unit cells in the established region of interest.
Abstract translation: 一种焦平面阵列，具有：多个检测器; 多个单元单元部分，每个部分由相应的检测器产生的电荷馈送以产生一系列帧; 以及多个存储部分组，每个部分耦合到相应的一个单位单元。 每组存储部分包括用于顺序存储帧的多个存储单元。 感兴趣区域选择器部分检查多个单元呼叫的帧，以检测具有预定特性的帧中的至少一个。 一种处理器：（i）识别靠近具有预定特征的检测单位单元的多个单位单元的子集，以建立感兴趣的区域; 以及（ii）顺序地读取在所建立的感兴趣区域中耦合到单位单元子集的存储部分中的多个存储单元。
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公开(公告)号：US11557235B1
公开(公告)日：2023-01-17
申请号：US17644542
申请日：2021-12-15
Applicant: Raytheon Company
Inventor： Jehyuk Rhee , Bryan W. Kean , John L. Vampola
Abstract: A device includes multiple row power lines and multiple row control lines arranged in rows, where each row control line corresponds to one of the row power lines. The device also includes multiple column power lines arranged in columns. The device further includes multiple unit cells, where each unit cell is coupled to one of the row power lines and one of the row control lines and selectively coupled to one of the column power lines. In addition, the device includes multiple row power switches and multiple column power switches arranged in pairs, where each pair includes one of the row power switches and one of the column power switches. Each pair is configured to selectively (i) connect a corresponding one of the rows and a corresponding one of the columns or (ii) isolate the corresponding one row and the corresponding one column from each other.
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Patent Agency Ranking
公开(公告)号：US20210226638A1
公开(公告)日：2021-07-22
申请号：US16749295
申请日：2020-01-22
Applicant: RAYTHEON COMPANY
Inventor： Richard E. Wahl , Joshua J. Cantrell , John L. Vampola , Micky R. Harris
Abstract: An analog counter circuit for use with a digital pixel includes: an input; an output; a first stage electrically coupled to the input that is charged to an initial charge voltage; a second stage that includes an accumulating charge storage device; and a charge transfer device between the first and second stages that includes a transfer voltage. The charge transfer device allows charge from the first stage to pass to the second stage and be accumulated on the accumulating charge storage device as long as a voltage at a node in the first stage is greater than the transfer voltage.
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27.发明授权公开(公告)号：US10834346B2
公开(公告)日：2020-11-10
申请号：US16426863
申请日：2019-05-30
Applicant: RAYTHEON COMPANY
Inventor： Steven Botts , Bryan W. Kean , Richard J. Peralta , John L. Vampola , Micky R. Harris
Abstract: A TDI scanner including a dynamically programmable focal plane array including a two-dimensional array of detectors arranged in a plurality of columns and a plurality of rows, the array being divided into a plurality of banks separated from one another by gap regions, each bank including a plurality of sub-banks, and each sub-bank including at least one row of detectors, a ROIC coupled to the focal plane array and configured to combine in a TDI process outputs from detectors in each column of detectors in each sub-bank, and a controller configured to program the focal plane array to selectively and dynamically set characteristics of the focal plane array, the characteristics including a size and a location within the two-dimensional array of each of the plurality of sub-banks and the gap regions, the size corresponding to a number of rows of detectors included in the respective sub-bank or gap region.
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公开(公告)号：US20190059775A1
公开(公告)日：2019-02-28
申请号：US16173442
申请日：2018-10-29
Applicant: Raytheon Company
Inventor： Matthew D. Chambers , John L. Vampola , Micky Harris
Abstract: A system including a detector array configured to receive electromagnetic (EM) radiation from a target object, the detector array having one or more detectors is disclosed. The system also includes a readout integrated circuit and one or more processors. The readout integrated circuit has a circuit comprising a number of detector boundary selection components, each one of the number of detector boundary selection components configured to select or adjust a detector boundary from least one of a sub-column boundary or an adjustable boundary.
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公开(公告)号：US20180190705A1
公开(公告)日：2018-07-05
申请号：US15856747
申请日：2017-12-28
Applicant: RAYTHEON COMPANY
Inventor： Sean P. Kilcoyne , John L. Vampola , Barry M. Starr , Chad W. Fulk , Christopher L. Mears , John J. Drab
IPC: H01L27/146 , H01L21/302 , H01L21/768
CPC classification number: H01L27/14636 , H01L21/302 , H01L21/76877 , H01L27/14623 , H01L27/14634 , H01L27/14643 , H01L27/14687 , H01L27/1469
Abstract: Aspects and examples described herein provide a hybrid imaging sensor chip assembly for reducing undesired radiative transfer between a complementary metal-oxide semiconductor (CMOS) read-out integrated circuit (ROIC) and an optical detector, and methods of manufacturing a hybrid imaging sensor chip assembly. In one example, a hybrid imaging sensor chip assembly includes an optical detector configured to collect electromagnetic radiation incident thereon, a complementary metal-oxide semiconductor (CMOS) read-out integrated circuit (ROIC), and a radiation-shielding wafer interposed between the optical detector and the CMOS ROIC, the radiation-shielding wafer including a plurality of through wafer vias (TWVs) electrically coupled to the optical detector and the CMOS ROIC, the radiation-shielding wafer being positioned to prevent radiative transfer between the CMOS ROIC and the optical detector.
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公开(公告)号：US20180184020A1
公开(公告)日：2018-06-28
申请号：US15388023
申请日：2016-12-22
Applicant: RAYTHEON COMPANY
Inventor： John L. Vampola , Micky R. Harris , Bryan W. Kean , Steven Botts , Richard J. Peralta
CPC classification number: H04N5/3559 , H04N5/3535 , H04N5/35527 , H04N5/3742 , H04N5/37452 , H04N5/378
Abstract: According to one aspect, embodiments herein provide a unit cell circuit comprising a photodetector configured to generate a photo-current in response to receiving light, a first integration capacitor configured to accumulate charge corresponding to the photo-current, a second integration capacitor configured to accumulate charge corresponding to the photo-current, a charge diverting switch coupled to the photodetector and configured to selectively couple the first integration capacitor to the second integration capacitor and divert the photo-current to the second integration capacitor in response to a voltage across the first integration capacitor exceeding a threshold level, and read-out circuitry coupled to the first integration capacitor and the charge diverting switch and configured to read-out a first voltage sample from the first integration capacitor corresponding to charge accumulated on the first integration capacitor and to read-out a second voltage sample from the second integration capacitor corresponding to charge accumulated on the second integration capacitor.
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