公开(公告)号：US20240194631A1

公开(公告)日：2024-06-13

申请号：US18444180

申请日：2024-02-16

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Keunhyuk LEE ,  Jerome TEYSSEYRE ,  Tiburcio A. MALDO

IPC: H01L23/00

CPC classification number: H01L24/72 ,  H01L24/90

Abstract: A clip preform includes a die contact portion and an aligner structure. An intermediate portion connects the die contact portion to a lead contact portion in the aligner structure. The die contact portion is configured to contact a semiconductor die. The aligner structure is configured to attach the lead contact portion to a lead post. The die contact portion, the intermediate portion, and the aligner structure form a structure of a primary clip for connecting the semiconductor die to the lead post. The clip preform is severable by removing parts of the die contact portion and the intermediate portion of the clip preform to form a secondary clip for connecting the semiconductor die to the lead post. The aligner structure, a remaining part of the die contact portion, and a remaining part of the intermediate portion of the clip preform form a structure of the secondary clip.

公开(公告)号：US20240088007A1

公开(公告)日：2024-03-14

申请号：US17931665

申请日：2022-09-13

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jonghwan BAEK ,  Jeonghyuk PARK ,  Seungwon IM ,  Keunhyuk LEE ,  Dukyong LEE

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00 ,  H01L25/16

CPC classification number: H01L23/49833 ,  H01L21/4825 ,  H01L21/4839 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49844 ,  H01L23/49861 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/162 ,  H01L25/50 ,  H01L2224/32225 ,  H01L2224/48139 ,  H01L2224/48145 ,  H01L2224/48175 ,  H01L2224/48225 ,  H01L2224/73265 ,  H01L2924/12036 ,  H01L2924/13055

Abstract: A package includes a first direct bonded metal (DBM) substrate, a first semiconductor die disposed on a top surface of the first DBM substrate, a second DBM substrate disposed at a height above the first DBM substrate, and a second semiconductor die disposed on a top surface of the second DBM substrate. A wire bond is made between the first semiconductor die disposed on the top surface of the first DBM substrate and the second semiconductor die disposed on the top surface of the second DBM substrate.

公开(公告)号：US20240030093A1

公开(公告)日：2024-01-25

申请号：US18479565

申请日：2023-10-02

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Leo GU ,  Sixin JI ,  Jie CHANG ,  Keunhyuk LEE ,  Yong LIU

IPC: H01L23/373 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/3735 ,  H01L24/32 ,  H01L21/4871 ,  H01L24/83 ,  H01L2224/83815 ,  H01L2224/32237

Abstract: In one general aspect, a method can include forming a recess and a mesa in a metal layer associated with a substrate, and disposing a first portion of a conductive-bonding component on the mesa and a second portion of the conductive-bonding component in the recess. The method can include disposing a semiconductor component on the conductive-bonding component such that the second portion of the conductive-bonding component is disposed between an edge of the semiconductor component and a bottom surface of the recess.

公开(公告)号：US20230019930A1

公开(公告)日：2023-01-19

申请号：US17806961

申请日：2022-06-15

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Inpil YOO ,  Jerome TEYSSEYRE ,  Oseob JEON ,  Keunhyuk LEE ,  Michael J. SEDDON

IPC: H01L23/44 ,  H05K7/20

Abstract: Implementations of a semiconductor package may include one or more power semiconductor die included in a die module; a first heat sink directly coupled to one or more source pads of the die module; a second heat sink directly coupled to one or more drain pads of the die module; a gate contact coupled with one or more gate pads of the die module; and a coating coupled directly to the die module. The gate contact may be configured to extend through an immersion cooling enclosure.

公开(公告)号：US20220208654A1

公开(公告)日：2022-06-30

申请号：US17136340

申请日：2020-12-29

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jonghwan BAEK ,  JeongHyuk PARK ,  Seungwon IM ,  Keunhyuk LEE

IPC: H01L23/495 ,  H01L23/00

Abstract: Implementations of semiconductor packages may include a substrate, a first die coupled on the substrate, and a lead frame coupled over the substrate. The lead frame may include a die attach pad. Implementations of semiconductor packages may also include a second die coupled on the die attach pad. The second die may overlap the first die.

公开(公告)号：US20210159157A1

公开(公告)日：2021-05-27

申请号：US16695582

申请日：2019-11-26

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Keunhyuk LEE ,  Tiburcio MALDO ,  Jerome TEYSSEYRE ,  ZhengQiao XU ,  Zhiling LIU

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: Implementations of semiconductor clips may include a die attach portion coupled to a step portion, a lead attach portion directly coupled to the step portion, a first alignment feature directly coupled to a first side of the lead attach portion, and a second alignment feature directly coupled to a second side of the lead attach portion. The second side may be opposite the first side. The lead attach portion may be in a plane substantially parallel with a plane formed by the die attach portion.

公开(公告)号：US20190214749A1

公开(公告)日：2019-07-11

申请号：US15865498

申请日：2018-01-09

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jie CHANG ,  Huibin CHEN ,  Tiburcio MALDO ,  Keunhyuk LEE

IPC: H01R12/58 ,  H01R13/03 ,  H05K3/30 ,  H01L23/495 ,  H01L23/498

Abstract: Implementations of semiconductor packages may include: one or more die electrically coupled to a lead frame. The lead frame may be included within a housing. The semiconductor package may also include a set of signal leads extending from the housing, a set of power leads extending from the housing, and a plurality of press fit pins each fixedly coupled to the set of signal leads and the set of power leads. The set of signal leads and the set of power leads may be configured to couple with a substrate.