公开(公告)号：US20240224507A1

公开(公告)日：2024-07-04

申请号：US18541625

申请日：2023-12-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongmin Kim ,  Taejin Park ,  Chansic Yoon ,  Kiseok Lee ,  Hongjun Lee

IPC: H10B12/00 ,  H01L29/417 ,  H01L29/423

CPC classification number: H10B12/34 ,  H01L29/41741 ,  H01L29/4236 ,  H10B12/315

Abstract: A semiconductor device includes an active pattern on a substrate, a gate structure, a conductive filling pattern and a bit line structure on the conductive filling pattern. The gate structure extends through an upper portion of the active pattern, and has an upper surface higher than an upper surface of the active pattern. The conductive filling pattern includes a lower portion on the active pattern and an upper portion thereon. The lower portion contacts an upper sidewall of the gate structure, and the upper portion has a width greater than a width of the lower portion.

公开(公告)号：US20240170574A1

公开(公告)日：2024-05-23

申请号：US18518264

申请日：2023-11-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joongchan Shin ,  Kiseok Lee ,  Seokhan Park ,  Seokho Shin

IPC: H01L29/78 ,  H10B12/00

CPC classification number: H01L29/7827 ,  H10B12/0335 ,  H10B12/482 ,  H10B12/50

Abstract: A semiconductor device includes a vertical channel transistor including a vertical channel region extending in a vertical direction and a cell gate electrode facing a first side surface of the vertical channel region. A bit line is electrically connected to the vertical channel transistor at a level that is lower than a level of the vertical channel transistor. A peripheral semiconductor body has at least a portion thereof disposed on a same level as the vertical channel region. Peripheral source/drain regions are disposed in the peripheral semiconductor body and are spaced apart from each other in a horizontal direction. A peripheral channel region is disposed between the peripheral source/drain regions in the peripheral semiconductor body. A peripheral gate is disposed below the peripheral semiconductor body. At least a portion of the peripheral gate is disposed on a same level as at least a portion of the bit line.

公开(公告)号：US20240074212A1

公开(公告)日：2024-02-29

申请号：US18236607

申请日：2023-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungeun Choi ,  Kiseok Lee

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B12/00

CPC classification number: H10B80/00 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B12/315 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: A method of fabricating a semiconductor device may use, as an internal contact region, a region in which a memory cell region overlaps a core and/or peripheral region by bonding at least a partial region of the memory cell region to at least a partial region of the core and/or peripheral region by a direct bonding method, and thus, even when an additional contact region is secured outside the memory cell region to be smaller, signals and/or power may be transmitted between the memory cell region and the core and/or peripheral region.

公开(公告)号：US11908797B2

公开(公告)日：2024-02-20

申请号：US17129083

申请日：2020-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiyoung Ahn ,  Seunguk Han ,  Sunghwan Kim ,  Seoryong Park ,  Kiseok Lee ,  Yoonyoung Choi ,  Taehee Han ,  Jiseok Hong

IPC: H01L23/528 ,  H01L29/06 ,  H10B12/00 ,  H01L23/522 ,  H01L21/768 ,  H01L21/764

CPC classification number: H01L23/5283 ,  H01L21/764 ,  H01L21/7682 ,  H01L29/0649 ,  H10B12/482 ,  H10B12/485 ,  H10B12/488 ,  H01L23/5222 ,  H10B12/0335 ,  H10B12/315 ,  H10B12/34

Abstract: An integrated circuit device is provided. The integrated circuit device includes: a bit line on a substrate, the bit line including a lower conductive layer and an upper conductive layer; an insulating capping pattern on the bit line; and a main insulating spacer on a sidewall of the bit line and a sidewall of the insulating capping pattern, the main insulating spacer including an extended portion that is convex toward the upper conductive layer.

公开(公告)号：US20230389287A1

公开(公告)日：2023-11-30

申请号：US18144885

申请日：2023-05-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byeongjoo Ku ,  Keunnam Kim ,  Kiseok Lee

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/482 ,  H10B12/488 ,  H10B12/50

Abstract: A semiconductor device includes: a substrate including a cell array area, a periphery circuit area, and an interface area; bit lines arranged in the cell array area and extending in a first horizontal direction; a mold insulating layer arranged on the bit lines and including openings extending in a second horizontal direction; channel layers respectively arranged on the bit lines in each of the openings; word lines respectively arranged on the channel layers and extending in the second horizontal direction from the cell array area to the interface area, the word lines including a first word line on a first sidewall of each opening of the mold insulating layer and a second word line on a second sidewall of the opening; and a trimming insulating block arranged in the interface area and connected to an end of the first word line and an end of the second word line.

公开(公告)号：US20230361215A1

公开(公告)日：2023-11-09

申请号：US18133730

申请日：2023-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyeom Kim ,  Daehong Ko ,  Jinbum Kim ,  Sangmoon Lee ,  Daeseop Byeon ,  Seran Park ,  Hyunsu Shin ,  Kiseok Lee ,  Chunghee Jo

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7851 ,  H01L29/66545 ,  H01L29/6656

Abstract: A semiconductor device including a substrate extending in a first direction and a second direction perpendicular to the first direction, a first active pattern protruding from a top surface of the substrate and extending in the first direction, an isolation pattern covering a sidewall of the first active pattern on the substrate, first silicon patterns spaced apart from each other in a third direction on the first active pattern, the third direction perpendicular to the first direction and second direction, a first source/drain layer extending in the third direction from a top surface of the first active pattern on the first active pattern, and in contact with sidewalls of the first silicon patterns, wherein a sidewall of the first source/drain layer in the second direction has a constant inclination with respect to the top surface of the substrate, and a gate structure extending in the second direction while filling a gap between the first silicon patterns on the substrate.

公开(公告)号：US20230301063A1

公开(公告)日：2023-09-21

申请号：US18094789

申请日：2023-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soobin Yim ,  Insu Kim ,  Seohyun Maeng ,  Kijong Park ,  Imsoo Park ,  Kiseok Lee

IPC: H10B12/00

CPC classification number: H10B12/30 ,  H10B12/05

Abstract: A semiconductor device may include first pillar insulation patterns on a substrate, second pillar insulation patterns on the substrate, silicon patterns stacked on the substrate to be spaced apart from each other in a vertical direction, a word line on each of upper and lower surfaces of each silicon pattern, a bit line contacting a first sidewall of at least a first silicon pattern of the silicon patterns, and a capacitor contacting a second sidewall of the first silicon pattern. Each of the first pillar insulation patterns may extend in the vertical direction from an upper surface of the substrate. The first pillar insulation patterns may be spaced apart from each other in a first direction, and may be aligned in a line. Each of the second pillar insulation patterns may extend in the vertical direction. The second pillar insulation patterns may be spaced apart from each other in the first direction, and may be aligned in a line. The second pillar insulation patterns and the first pillar insulation patterns may overlap with each other in a second direction perpendicular to the first direction. Each of the silicon patterns may extend in the second direction and be positioned between two first pillar insulation patterns and between two second pillar insulation patterns, and each of the silicon patterns may include two sidewalls opposite each other in the first direction and having a straight line shape. Each word line may extend in the first direction to cross the silicon patterns. Each word line may contact a sidewall of at least one insulation pattern of the first pillar insulation patterns and/or at least one insulation pattern of the second pillar insulation patterns. The bit line may extend in the vertical direction. The capacitor may be disposed in a horizontal direction to have a dielectric layer horizontally between a lower electrode and an upper electrode.

公开(公告)号：US11647625B2

公开(公告)日：2023-05-09

申请号：US17191308

申请日：2021-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeho Hong ,  Kyunghwan Lee ,  Hyuncheol Kim ,  Huijung Kim ,  Hyunmog Park ,  Kiseok Lee ,  Minhee Cho

IPC: H01L27/108 ,  G11C5/06 ,  H01L29/24

CPC classification number: H01L27/1082 ,  G11C5/063 ,  H01L27/10858 ,  H01L27/10873 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891 ,  H01L29/24

Abstract: A memory device is provided. The memory device includes: a substrate; a memory unit provided on the substrate; a channel provided on the memory unit; a word line surrounded by the channel and extending in a first horizontal direction; a gate insulating layer interposed between the channel and the word line; and a bit line contacting an upper end of the channel and extending in a second horizontal direction that crosses the first horizontal direction.

公开(公告)号：US20220278121A1

公开(公告)日：2022-09-01

申请号：US17748261

申请日：2022-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok Lee ,  Junsoo Kim ,  Hui-Jung Kim ,  Bong-Soo Kim ,  Satoru Yamada ,  Kyupil Lee ,  Sunghee Han ,  HyeongSun Hong ,  Yoosang Hwang

IPC: H01L27/11556 ,  H01L23/532 ,  G11C7/18 ,  H01L49/02 ,  G11C8/14 ,  H01L27/11524

Abstract: A semiconductor memory device includes a stack structure including a plurality of layers vertically stacked on a substrate. Each of the plurality of layers includes a first dielectric layer, a semiconductor layer, and a second dielectric layer that are sequentially stacked, and a first conductive line in the second dielectric layer and extending in a first direction. The device also includes a second conductive line extending vertically through the stack structure, and a capacitor in the stack structure and spaced apart from the second conductive line. The semiconductor layer includes semiconductor patterns extending in a second direction intersecting the first direction between the first conductive line and the substrate. The second conductive line is between a pair of the semiconductor patterns adjacent to each other in the first direction. An end of each of the semiconductor patterns is electrically connected to a first electrode of the capacitor.

公开(公告)号：US11411007B2

公开(公告)日：2022-08-09

申请号：US16991661

申请日：2020-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu Lee ,  Kiseok Lee ,  Woobin Song ,  Minhee Cho

IPC: H01L27/108 ,  G11C11/408 ,  G11C11/4094

Abstract: A semiconductor memory device includes a memory cell array of a three-dimensional structure including a plurality of memory cells repeatedly arranged in a first horizontal direction and a second horizontal direction that are parallel with a main surface of a substrate and cross each other on the substrate and in a vertical direction perpendicular to the main surface, wherein each of the plurality of memory cells includes three transistors. A method of manufacturing a semiconductor memory device includes forming simultaneously a plurality of memory cells arranged in a row in a vertical direction on a substrate, wherein each of the plurality of memory cells includes three transistors.