公开(公告)号：US10381380B2

公开(公告)日：2019-08-13

申请号：US15947853

申请日：2018-04-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Fu Hsu ,  Chun-Yuan Wu

IPC: H01L29/22 ,  H01L29/786 ,  H01L27/12 ,  H01L29/51 ,  H01L29/24 ,  H01L23/528 ,  H01L29/66 ,  H01L21/02 ,  H01L21/441 ,  H01L21/768 ,  H01L29/423 ,  H01L29/49

Abstract: The present invention provides a method of forming a semiconductor device. First, a substrate having a first insulating layer formed thereon is provided. After forming an oxide semiconductor layer on the first insulating layer, two source/drain regions are formed on the oxide semiconductor layer. A bottom oxide layer is formed to entirely cover the source/drain regions, following by forming a high-k dielectric layer on the bottom oxide layer. Next, a thermal process is performed on the high-k dielectric layer, and a plasma treatment is performed on the high-k dielectric layer in the presence of a gas containing an oxygen element.

公开(公告)号：US20190115352A1

公开(公告)日：2019-04-18

申请号：US16216954

申请日：2018-12-11

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chien-Ting Ho ,  Shih-Fang Tzou ,  Chun-Yuan Wu ,  Li-Wei Feng ,  Yu-Chieh Lin ,  Ying-Chiao Wang ,  Tsung-Ying Tsai

IPC: H01L27/105 ,  H01L21/311 ,  H01L21/768 ,  H01L21/02 ,  H01L29/66 ,  H01L27/108

Abstract: A semiconductor device includes a memory region, a plurality of bit lines in the memory region, a first low-k dielectric layer on each sidewall of each bit line, a plurality of storage node regions between the bit lines, and a second low-k dielectric layer surrounding each storage node region.

公开(公告)号：US20190006519A1

公开(公告)日：2019-01-03

申请号：US15637773

申请日：2017-06-29

Applicant: United Microelectronics Corp.

Inventor： Yen-Chen Chen ,  Xiao Wu ,  Hai Tao Liu ,  Ming Hua Du ,  Shouguo Zhang ,  Yao-Hung Liu ,  Chin-Fu Lin ,  Chun-Yuan Wu

IPC: H01L29/786 ,  H01L29/24 ,  H01L29/66 ,  H01L29/45

CPC classification number: H01L29/7869 ,  H01L29/24 ,  H01L29/45 ,  H01L29/66969

Abstract: A semiconductor device includes an oxide semiconductor layer, disposed over a substrate. A source electrode of a metal nitride is disposed on the oxide semiconductor layer. A drain electrode of the metal nitride is disposed on the oxide semiconductor layer. A metal-nitride oxidation layer is formed on a surface of the source electrode and the drain electrode. A ratio of a thickness of the metal-nitride oxidation layer to a thickness of the drain electrode or the source electrode is equal to or less than 0.2.

公开(公告)号：US20180323256A1

公开(公告)日：2018-11-08

申请号：US16040319

申请日：2018-07-19

Applicant: United Microelectronics Corp.

Inventor： Huai-Tzu Chiang ,  Sheng-Hao Lin ,  Hao-Ming Lee ,  Yu-Ru Yang ,  Shih-Hsien Huang ,  Chien-Hung Chen ,  Chun-Yuan Wu ,  Cheng-Tzung Tsai

IPC: H01L29/06 ,  H01L29/10 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L21/225

CPC classification number: H01L29/0615 ,  H01L21/2253 ,  H01L21/76802 ,  H01L21/76871 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

Abstract: Provided is a FinFET including a substrate, at least one fin and at least one gate. A portion of the at least one fin is embedded in the substrate. The at least one fin includes, from bottom to top, a seed layer, a stress relaxation layer and a channel layer. The at least one gate is across the at least one fin. A method of forming a FinFET is further provided.

公开(公告)号：US20180053826A1

公开(公告)日：2018-02-22

申请号：US15797011

申请日：2017-10-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Hung Chen ,  Shih-Hsien Huang ,  Yu-Ru Yang ,  Huai-Tzu Chiang ,  Hao-Ming Lee ,  Sheng-Hao Lin ,  Cheng-Tzung Tsai ,  Chun-Yuan Wu

IPC: H01L29/165 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L21/3065 ,  H01L29/06 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L29/165 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/30604 ,  H01L21/3065 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device comprises a semiconductor substrate and a semiconductor fin. The semiconductor substrate has an upper surface and a recess extending downwards into the semiconductor substrate from the upper surface. The semiconductor fin is disposed in the recess and extends upwards beyond the upper surface, wherein the semiconductor fin is directly in contact with semiconductor substrate, so as to form at least one semiconductor hetero-interface on a sidewall of the recess.

公开(公告)号：US20170141232A1

公开(公告)日：2017-05-18

申请号：US15368647

申请日：2016-12-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Fu Hsu ,  Chun-Yuan Wu

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L29/7869 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/78696

Abstract: The present invention provides a semiconductor structure, including a base, a patterned oxide semiconductor (OS) layer, two source/drain regions, a protective layer, a gate layer and a gate dielectric layer. The patterned OS layer is disposed on the base. Two source/drain regions are disposed on the patterned OS layer and are separated by a recess. Each source/drain region includes an inner sidewall facing the recess and an outer sidewall opposite to the inner sidewall. The protective layer is disposed on a sidewall of the patterned OS layer but is not on the inner sidewall of the source/drain region. The gate layer is disposed on the patterned OS layer, and the gate dielectric layer is disposed between the gate layer and the patterned OS layer.

公开(公告)号：US09608126B1

公开(公告)日：2017-03-28

申请号：US14953036

申请日：2015-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Fu Hsu ,  Chun-Yuan Wu ,  Xu Yang Shen ,  Zhibiao Zhou ,  Qinggang Xing

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/78696

Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a substrate, an interconnect structure, and an oxide semiconductor structure. The substrate has a first region and a second region. The interconnect structure is disposed on the substrate, in the first region. The oxide semiconductor structure is disposed over a hydrogen blocking layer, in the second region of the substrate.

公开(公告)号：US09543448B1

公开(公告)日：2017-01-10

申请号：US14929396

申请日：2015-11-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Fu Hsu ,  Chun-Yuan Wu

IPC: H01L29/10 ,  H01L29/786 ,  H01L29/66 ,  H01L29/40 ,  H01L29/45

CPC classification number: H01L29/7869 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/78696

Abstract: The present invention provides a semiconductor structure, including a base, a patterned oxide semiconductor (OS) layer, two source/drain regions, a protective layer, a gate layer and a gate dielectric layer. The patterned OS layer is disposed on the base. Two source/drain regions are disposed on the patterned OS layer and are separated by a recess. Each source/drain region includes an inner sidewall facing the recess and an outer sidewall opposite to the inner sidewall. The protective layer is disposed on a sidewall of the patterned OS layer but is not on the inner sidewall of the source/drain region. The gate layer is disposed on the patterned OS layer, and the gate dielectric layer is disposed between the gate layer and the patterned OS layer. The present invention further provides a method of forming the same.

Abstract translation: 本发明提供一种半导体结构，包括基底，图案化氧化物半导体（OS）层，两个源极/漏极区，保护层，栅极层和栅极介电层。 图案化的OS层设置在基底上。 两个源极/漏极区域设置在图案化的OS层上并由凹槽分开。 每个源极/漏极区域包括面向凹部的内侧壁和与内侧壁相对的外侧壁。 保护层设置在图案化的OS层的侧壁上，但不在源/漏区的内侧壁上。 栅极层设置在图案化的OS层上，并且栅极介电层设置在栅极层和图案化的OS层之间。 本发明还提供一种形成该方法的方法。

公开(公告)号：US09466727B1

公开(公告)日：2016-10-11

申请号：US14925984

申请日：2015-10-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Fu Hsu ,  Chun-Yuan Wu

IPC: H01L21/44 ,  H01L29/786 ,  H01L29/66 ,  H01L21/768 ,  H01L23/535 ,  H01L23/532

CPC classification number: H01L29/7869 ,  H01L21/76831 ,  H01L21/8258 ,  H01L23/485 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/1207 ,  H01L29/66659 ,  H01L29/66969 ,  H01L29/7833 ,  H01L29/78648 ,  H01L29/78696

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a metal-oxide-semiconductor (MOS) transistor, a plug, a hydrogen blocking layer and an oxide semiconductor (OS) structure. The MOS transistor is disposed on the substrate, and the plug is disposed on the MOS transistor to electrically connect thereto. The hydrogen blocking layer is disposed only on sidewalls of the plug, wherein the hydrogen blocking layer includes a high-k dielectric layer. The OS structure is disposed on the substrate, wherein the OS structure includes an oxide semiconductor layer.

Abstract translation: 半导体器件及其形成方法，半导体器件包括衬底，金属氧化物半导体（MOS）晶体管，插塞，氢阻挡层和氧化物半导体（OS）结构。 MOS晶体管设置在基板上，并且插头设置在MOS晶体管上以与其电连接。 氢阻挡层仅设置在插塞的侧壁上，其中氢阻挡层包括高k电介质层。 OS结构设置在基板上，其中OS结构包括氧化物半导体层。

公开(公告)号：US09281201B2

公开(公告)日：2016-03-08

申请号：US14029824

申请日：2013-09-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ted Ming-Lang Guo ,  Chiu-Hsien Yeh ,  Chin-Cheng Chien ,  Chun-Yuan Wu

IPC: H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/321 ,  H01L21/3213

CPC classification number: H01L21/28176 ,  H01L21/321 ,  H01L21/32134 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7833

Abstract: A method of manufacturing a semiconductor device having a metal gate is provided. A substrate having a first conductive type transistor and a second conductive type transistor formed thereon is provided. The first conductive type transistor has a first trench and the second conductive type transistor has a second trench. A first work function layer is formed in the first trench. A hardening process is performed for the first work function layer. A softening process is performed for a portion of the first work function layer. A pull back step is performed to remove the portion of the first work function layer. A second work function layer is formed in the second trench. A low resistive metal layer is formed in the first trench and the second trench.

Abstract translation: 提供一种制造具有金属栅极的半导体器件的方法。 提供具有形成在其上的第一导电型晶体管和第二导电型晶体管的衬底。 第一导电型晶体管具有第一沟槽，第二导电型晶体管具有第二沟槽。 在第一沟槽中形成第一功函数层。 对第一功函数层进行硬化处理。 对第一功函数层的一部分进行软化处理。 执行拉回步骤以去除第一功函数层的部分。 在第二沟槽中形成第二功函数层。 在第一沟槽和第二沟槽中形成低电阻金属层。