公开(公告)号：US10722998B2

公开(公告)日：2020-07-28

申请号：US15719515

申请日：2017-09-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Chieh Hsu ,  Fu-Shou Tsai ,  Kun-Ju Li ,  Po-Cheng Huang ,  Chun-Liang Liu

IPC: B24B37/24 ,  B24B37/22 ,  B24B37/26

Abstract: The present invention provides a wafer polishing pad, the wafer polishing pad includes a polishing material layer, a plurality of recesses are formed on the top surface of the polishing material layer, and a warning element disposed within the polishing material layer, the warning element and the polishing material layer have different colors. The feature of the invention is that forming a warning element in the polishing material layer, when the visible state of the warning element is changed, for example, when the warning element appears, disappears or changes the shapes, it means that the wafer polishing pad needs to be replaced. In this way, the user can confirm the destroying situation of the wafer polishing pad easily, and also improving the manufacturing process efficiency.

公开(公告)号：US20190070706A1

公开(公告)日：2019-03-07

申请号：US15719515

申请日：2017-09-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Chieh Hsu ,  Fu-Shou Tsai ,  Kun-Ju Li ,  Po-Cheng Huang ,  Chun-Liang Liu

IPC: B24B37/22 ,  B24B37/26

CPC classification number: B24B37/22 ,  B24B37/24 ,  B24B37/26 ,  B24D2205/00

Abstract: The present invention provides a wafer polishing pad, the wafer polishing pad includes a polishing material layer, a plurality of recesses are formed on the top surface of the polishing material layer, and a warning element disposed within the polishing material layer, the warning element and the polishing material layer have different colors. The feature of the invention is that forming a warning element in the polishing material layer, when the visible state of the warning element is changed, for example, when the warning element appears, disappears or changes the shapes, it means that the wafer polishing pad needs to be replaced. In this way, the user can confirm the destroying situation of the wafer polishing pad easily, and also improving the manufacturing process efficiency.

公开(公告)号：US20190043866A1

公开(公告)日：2019-02-07

申请号：US16151337

申请日：2018-10-03

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yu-Ting Li ,  Jen-Chieh Lin ,  Wen-Chin Lin ,  Po-Cheng Huang ,  Fu-Shou Tsai

IPC: H01L27/108

Abstract: A semiconductor IC structure includes a substrate including at least a memory cell region and a peripheral region defined thereon, a plurality of memory cells formed in the memory cell region, at least an active device formed in the peripheral region, a plurality of contact plugs formed in the memory cell region, and at least a bit line formed in the memory cell region. The contact plugs are physically and electrically connected to the bit line. More important, bottom surfaces of the contact plugs are lower a surface of the substrate.

公开(公告)号：US10128251B2

公开(公告)日：2018-11-13

申请号：US15261845

申请日：2016-09-09

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yu-Ting Li ,  Jen-Chieh Lin ,  Wen-Chin Lin ,  Po-Cheng Huang ,  Fu-Shou Tsai

IPC: H01L27/10 ,  H01L27/108

Abstract: A semiconductor IC structure includes a substrate including at least a memory cell region and a peripheral region defined thereon, a plurality of memory cells formed in the memory cell region, at least an active device formed in the peripheral region, a plurality of contact plugs formed in the memory cell region, and at least a bit line formed in the memory cell region. The contact plugs are physically and electrically connected to the bit line. More important, bottom surfaces of the contact plugs are lower a surface of the substrate.

公开(公告)号：US10049887B2

公开(公告)日：2018-08-14

申请号：US15678117

申请日：2017-08-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Chieh Hsu ,  Fu-Shou Tsai ,  Yu-Ting Li ,  Yi-Liang Liu ,  Kun-Ju Li

IPC: H01L21/3105 ,  H01L29/06 ,  H01L29/78

Abstract: A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A photoresist pattern is formed on the material layer. The photoresist pattern masks the second region, while exposes at least a portion of the first region. At least a portion of the material layer not covered by the photoresist pattern is etched away. A polish stop layer is deposited on the material layer. A cap layer is deposited on the polish stop layer. A chemical mechanical polishing (CMP) process is performed to polish the cap layer.

公开(公告)号：US20180076205A1

公开(公告)日：2018-03-15

申请号：US15261845

申请日：2016-09-09

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yu-Ting Li ,  Jen-Chieh Lin ,  Wen-Chin Lin ,  Po-Cheng Huang ,  Fu-Shou Tsai

IPC: H01L27/108

CPC classification number: H01L27/10888 ,  H01L27/10823 ,  H01L27/10885 ,  H01L27/10894

Abstract: A semiconductor IC structure includes a substrate including at least a memory cell region and a peripheral region defined thereon, a plurality of memory cells formed in the memory cell region, at least an active device formed in the peripheral region, a plurality of contact plugs formed in the memory cell region, and at least a bit line formed in the memory cell region. The contact plugs are physically and electrically connected to the bit line. More important, bottom surfaces of the contact plugs are lower a surface of the substrate.

公开(公告)号：US20180033636A1

公开(公告)日：2018-02-01

申请号：US15221586

申请日：2016-07-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Chieh Hsu ,  Fu-Shou Tsai ,  Yu-Ting Li ,  Po-Cheng Huang ,  Yi-Liang Liu ,  Wen-Chin Lin ,  Chun-Yi Wang ,  Chun-Yuan Wu

IPC: H01L21/3105 ,  H01L21/02

CPC classification number: H01L21/31053 ,  H01L21/02065 ,  H01L21/32115 ,  H01L21/823431

Abstract: A method of fabricating a semiconductor structure is provided. A substrate surface is provided and a first layer is disposed on the substrate surface. A second layer covering the first layer is formed wherein the materials of the first layer and the second layer are different. A first polishing operation is performed on the second layer until a first polished surface exposing a portion of the first layer is obtained. A second polishing operation is performed on the first polished surface to obtain a second polished surface wherein an upper portion of the exposed portion of the first layer is removed. None of the substrate is exposed from the first polished surface and the second polished surface.

公开(公告)号：US20170162402A1

公开(公告)日：2017-06-08

申请号：US14960977

申请日：2015-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Shou Tsai ,  Yu-Ting Li ,  Li-Chieh Hsu ,  Kun-Ju Li ,  Chih-Hsun Lin ,  Po-Cheng Huang ,  Yi-Liang Liu ,  Wen-Chin Lin

IPC: H01L21/321 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L21/3212 ,  H01L21/0217 ,  H01L21/31053 ,  H01L21/7684

Abstract: A method of manufacturing a semiconductor structure is provided. First, a preliminary structure is provided. The preliminary structure has a first region and a second region, and the preliminary structure comprises a plurality of features in the first region. Then, a first polish stop layer is formed on the preliminary structure. The first polish stop layer comprises a concave portion in the second region, and the concave portion defines an opening. A first overlying layer is formed on the first polish stop layer. Thereafter, a second polish stop layer is formed on the first overlying layer. The second polish stop layer has a graduated change in composition. The second polish stop layer comprises a concave portion at least partially formed in the opening. A second overlying layer is formed on the second polish stop layer.

公开(公告)号：US20230051000A1

公开(公告)日：2023-02-16

申请号：US17494809

申请日：2021-10-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ang Chan ,  Hsin-Jung Liu ,  Kun-Ju Li ,  Chau-Chung Hou ,  Fu-Shou Tsai ,  Yu-Lung Shih ,  Jhih-Yuan Chen ,  Chun-Han Chen ,  Wei-Xin Gao ,  Shih-Ming Lin

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: A semiconductor structure includes a first dielectric layer on a substrate, a conductive structure disposed in the first dielectric layer and including a terminal portion and an extending portion connecting the terminal portion and extending away from the terminal portion, a second dielectric layer disposed on the first dielectric layer, a conductive via through the second dielectric layer and directly contacting the extending portion, and a dummy via through the second dielectric layer and directly contacting the terminal portion. In a cross-sectional view, a width of the dummy via is smaller than 50% of a width of the conductive via.

公开(公告)号：US10943910B2

公开(公告)日：2021-03-09

申请号：US16151337

申请日：2018-10-03

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yu-Ting Li ,  Jen-Chieh Lin ,  Wen-Chin Lin ,  Po-Cheng Huang ,  Fu-Shou Tsai

IPC: H01L27/10 ,  H01L27/108 ,  H01L27/06 ,  H01L21/8234

Abstract: A semiconductor IC structure includes a substrate including at least a memory cell region and a peripheral region defined thereon, a plurality of memory cells formed in the memory cell region, at least an active device formed in the peripheral region, a plurality of contact plugs formed in the memory cell region, and at least a bit line formed in the memory cell region. The contact plugs are physically and electrically connected to the bit line. More important, bottom surfaces of the contact plugs are lower a surface of the substrate.