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    Method for manufacturing metal interconnects
    22.
    发明授权
    Method for manufacturing metal interconnects 有权

    公开(公告)号：US09779989B1

    公开(公告)日：2017-10-03

    申请号：US15168095

    申请日：2016-05-30

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Po-Cheng Huang ,  Chun-Liang Liu

    IPC: H01L21/00 ,  H01L21/768

    CPC classification number: H01L21/7684 ,  H01L21/76843 ,  H01L21/76862 ,  H01L21/76873

    Abstract: A method for manufacturing metal interconnects. The method includes following steps. A substrate including a dielectric layer formed thereon is provided, and a plurality of trenches are formed in the dielectric layer. Next, a seed layer is formed in the trenches and on the dielectric layer and followed by masking regions of the seed layer to define a plurality of masked regions and a plurality of exposed regions for the seed layer. Subsequently, a surface treatment is performed to the exposed regions of the seed layer to form a plurality of rough surfaces on the exposed regions of the seed layer. Then, a metal layer is formed on the substrate, and the trenches are filled up with the metal layer.

    SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF
    24.
    发明申请
    SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF 审中-公开
    半导体结构及其工艺

    公开(公告)号：US20160336269A1

    公开(公告)日：2016-11-17

    申请号：US14709500

    申请日：2015-05-12

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Kun-Ju Li ,  Shu Min Huang ,  Kuo-Chin Hung ,  Po-Cheng Huang ,  Yu-Ting Li ,  Pei-Yu Lee ,  Min-Chuan Tsai ,  Chih-Hsun Lin ,  Wu-Sian Sie ,  Jen-Chieh Lin

    IPC: H01L23/535 ,  H01L21/768 ,  H01L23/532

    CPC classification number: H01L21/7684 ,  H01L21/28088 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76874 ,  H01L23/485 ,  H01L23/53266 ,  H01L29/66545 ,  H01L29/7833

    Abstract: A semiconductor process includes the following steps. A dielectric layer having a recess is formed on a substrate. A barrier layer is formed to cover the recess, thereby the barrier layer having two sidewall parts. A conductive layer is formed on the barrier layer by an atomic layer deposition process, thereby the conductive layer having two sidewall parts. The two sidewall parts of the conductive layer are pulled down. A conductive material fills the recess and has a part contacting the two sidewall parts of the barrier layer protruding from the two sidewall parts of the conductive layer, wherein the equilibrium potential difference between the barrier layer and the conductive layer is different from the equilibrium potential difference between the barrier layer and the conductive material. Moreover, the present invention also provides a semiconductor structure formed by said semiconductor process.

    Abstract translation: 半导体工艺包括以下步骤。 在基板上形成具有凹部的电介质层。 形成阻挡层以覆盖凹部，由此阻挡层具有两个侧壁部分。 通过原子层沉积工艺在阻挡层上形成导电层，由此导电层具有两个侧壁部分。 导电层的两个侧壁部分被拉下。 导电材料填充凹部，并且具有接触从导电层的两个侧壁部分突出的阻挡层的两个侧壁部分的部分，其中阻挡层和导电层之间的平衡电位差不同于平衡电位差 在阻挡层和导电材料之间。 此外，本发明还提供了由所述半导体工艺形成的半导体结构。

    METHOD OF FORMING SEMICONDUCTOR DEVICE
    26.
    发明申请
    METHOD OF FORMING SEMICONDUCTOR DEVICE 有权
    形成半导体器件的方法

    公开(公告)号：US20160099179A1

    公开(公告)日：2016-04-07

    申请号：US14506009

    申请日：2014-10-03

    Applicant: United Microelectronics Corp.

    Inventor： Chun-Tsen Lu ,  Chih-Jung Su ,  Jian-Wei Chen ,  Shui-Yen Lu ,  Yi-Wen Chen ,  Po-Cheng Huang ,  Chen-Ming Huang ,  Shih-Fang Tzou

    IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/311 ,  H01L21/02 ,  H01L29/06 ,  H01L21/3105

    CPC classification number: H01L29/66545 ,  H01L21/0206 ,  H01L21/02065 ,  H01L21/02271 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/311 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/4966 ,  H01L29/517

    Abstract: A method of forming a semiconductor device is disclosed. A substrate having multiple fins is provided. An insulating layer fills a lower portion of a gap between two adjacent fins. At least one first stacked structure is formed on one fin and at least one second stacked structure is formed on one insulation layer. A first dielectric layer is formed to cover the first and second stacked structures. A portion of the first dielectric layer and portions of the first and second stacked structures are removed. Another portion of the first dielectric layer is removed until a top of the remaining first dielectric layer is lower than tops of the first and second stacked structures. A second dielectric layer is formed to cover the first and second stacked structures. A portion of the second dielectric layer is removed until the tops of the first and second stacked structures are exposed.

    Abstract translation: 公开了一种形成半导体器件的方法。 提供具有多个翅片的基板。 绝缘层填充两个相邻翅片之间的间隙的下部。 在一个翅片上形成至少一个第一堆叠结构，并且在一个绝缘层上形成至少一个第二堆叠结构。 形成第一电介质层以覆盖第一和第二堆叠结构。 去除第一电介质层的一部分和第一和第二堆叠结构的部分。 去除第一电介质层的另一部分，直到剩余的第一电介质层的顶部低于第一和第二堆叠结构的顶部。 形成第二电介质层以覆盖第一和第二堆叠结构。 去除第二电介质层的一部分直到第一和第二堆叠结构的顶部露出。

    METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE
    27.
    发明申请
    METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE 有权
    形成半导体结构的方法

    公开(公告)号：US20150147874A1

    公开(公告)日：2015-05-28

    申请号：US14088445

    申请日：2013-11-25

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Po-Cheng Huang ,  I-Ming Tseng ,  Yu-Ting Li ,  Chun-Hsiung Wang ,  Wu-Sian Sie ,  Yi-Liang Liu ,  Chia-Lin Hsu ,  Po-Chao Tsao ,  Chien-Ting Lin ,  Shih-Fang Tzou

    IPC: H01L21/8234 ,  H01L21/265

    CPC classification number: H01L21/823431 ,  H01L21/265 ,  H01L21/3086 ,  H01L29/6681

    Abstract: The present invention provides a manufacturing method for forming a semiconductor structure, in which first, a substrate is provided, a hard mask is disposed on the substrate, the hard mask is then patterned to form a plurality of fin hard masks and a plurality of dummy fin hard masks, afterwards, a pattern transferring process is performed, to transfer the patterns of the fin hard masks and the fin hard masks into the substrate, so as to form a plurality of fin groups and a plurality of dummy fins. Each dummy fin is disposed on the end side of one fin group, and a fin cut process is performed, to remove each dummy fin.

    Abstract translation: 本发明提供一种用于形成半导体结构的制造方法，其中首先设置基板，在基板上设置硬掩模，然后将硬掩模图案化以形成多个散热片硬掩模和多个虚拟 翅片硬掩模，然后进行图案转印处理，将翅片硬掩模和翅片硬掩模的图案转移到基板中，以形成多个翅片组和多个虚拟翅片。 每个假翅片设置在一个翅片组的端侧，并进行翅片切割处理，以去除每个假翅片。

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