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    Magnetic tunnel junction (MTJ) device and forming method thereof
    21.
    发明授权
    Magnetic tunnel junction (MTJ) device and forming method thereof 有权

    公开(公告)号：US11545521B2

    公开(公告)日：2023-01-03

    申请号：US17157952

    申请日：2021-01-25

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wei Chen ,  Hui-Lin Wang ,  Yu-Ru Yang ,  Chin-Fu Lin ,  Yi-Syun Chou ,  Chun-Yao Yang

    IPC: H01L27/22 ,  H01L23/552 ,  H01L43/10 ,  H01F41/34 ,  H01L43/02 ,  G11C11/16 ,  H01F10/32 ,  H01L43/12

    Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a magnetic shielding layer. The two magnetic tunnel junction elements are arranged side by side. The magnetic shielding layer is disposed between the magnetic tunnel junction elements. A method of forming said magnetic tunnel junction (MTJ) device includes the following steps. An interlayer including a magnetic shielding layer is formed. The interlayer is etched to form recesses in the interlayer. The magnetic tunnel junction elements fill in the recesses. Or, a method of forming said magnetic tunnel junction (MTJ) device includes the following steps. A magnetic tunnel junction layer is formed. The magnetic tunnel junction layer is patterned to form magnetic tunnel junction elements. An interlayer including a magnetic shielding layer is formed between the magnetic tunnel junction elements.

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    24.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20170200721A1

    公开(公告)日：2017-07-13

    申请号：US15045258

    申请日：2016-02-17

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chien-Hung Chen ,  Shih-Hsien Huang ,  Yu-Ru Yang ,  Chia-Hsun Tseng ,  Cheng-Tzung Tsai ,  Chun-Yuan Wu

    IPC: H01L27/092 ,  H01L21/02 ,  H01L21/306 ,  H01L29/165 ,  H01L21/8238

    Abstract: A semiconductor device includes a substrate, a first well formed in the substrate, a second well formed in the substrate, a first fin formed on the first well, and a second fin formed on the second well. The first well includes a first conductivity type, the second well includes a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other. The substrate includes a first semiconductor material. The first fin and the second fin include the first semiconductor material and a second semiconductor material. A lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The first semiconductor material in the first fin includes a first concentration, the first semiconductor material in the second fin includes a second concentration, and the second concentration is larger than the first concentration.

    METHOD OF FORMING INTEGRATED CIRCUIT HAVING PLURAL TRANSISTORS WITH WORK FUNCTION METAL GATE STRUCTURES
    26.
    发明申请
    METHOD OF FORMING INTEGRATED CIRCUIT HAVING PLURAL TRANSISTORS WITH WORK FUNCTION METAL GATE STRUCTURES 有权
    形成具有工作功能的多晶硅晶体管的集成电路的方法金属栅结构

    公开(公告)号：US20160190019A1

    公开(公告)日：2016-06-30

    申请号：US15060572

    申请日：2016-03-03

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chih-Wei Yang ,  Yu-Feng Liu ,  Jian-Cun Ke ,  Chia-Fu Hsu ,  Yu-Ru Yang ,  En-Chiuan Liou

    IPC: H01L21/8238 ,  H01L29/423 ,  H01L21/28 ,  H01L29/49

    CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7833

    Abstract: The present invention provides a method of forming an integrated circuit including a substrate, a first transistor, a second transistor and a third transistor. The first transistor has a first metal gate including a first bottom barrier layer, a first work function metal layer and a first metal layer. The second transistor has a second metal gate including a second bottom barrier layer, a second work function metal layer and a second metal layer. The third transistor has a third metal gate including a third bottom barrier layer, a third work function metal layer and a third metal layer. The first transistor, the second transistor and the third transistor has the same conductive type. A nitrogen concentration of the first bottom barrier layer>a nitrogen concentration of the second bottom barrier layer>a nitrogen concentration of the third bottom barrier layer.

    Abstract translation: 本发明提供一种形成包括衬底，第一晶体管，第二晶体管和第三晶体管的集成电路的方法。 第一晶体管具有包括第一底部阻挡层，第一功函数金属层和第一金属层的第一金属栅极。 第二晶体管具有包括第二底部阻挡层，第二功函数金属层和第二金属层的第二金属栅极。 第三晶体管具有包括第三底部阻挡层，第三功函数金属层和第三金属层的第三金属栅极。 第一晶体管，第二晶体管和第三晶体管具有相同的导电类型。 第一底部阻挡层的氮浓度>第二底部阻挡层的氮浓度>第三底部阻挡层的氮浓度。

    Integrated circuit having plural transistors with work function metal gate structures
    27.
    发明授权
    Integrated circuit having plural transistors with work function metal gate structures 有权
    具有多个具有功函数金属栅结构的晶体管的集成电路

    公开(公告)号：US09318389B1

    公开(公告)日：2016-04-19

    申请号：US14520342

    申请日：2014-10-22

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chih-Wei Yang ,  Yu-Feng Liu ,  Jian-Cun Ke ,  Chia-Fu Hsu ,  Yu-Ru Yang ,  En-Chiuan Liou

    IPC: H01L21/82 ,  H01L27/08 ,  H01L29/49 ,  H01L29/40 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423

    CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7833

    Abstract: The present invention provides an integrated circuit including a substrate, a first transistor, a second transistor and a third transistor. The first transistor has a first metal gate including a first bottom barrier layer, a first work function metal layer and a first metal layer. The second transistor has a second metal gate including a second bottom barrier layer, a second work function metal layer and a second metal layer. The third transistor has a third metal gate including a third bottom barrier layer, a third work function metal layer and a third metal layer. The first transistor, the second transistor and the third transistor has the same conductive type. A nitrogen concentration of the first bottom barrier layer>a nitrogen concentration of the second bottom barrier layer>a nitrogen concentration of the third bottom barrier layer.

    Abstract translation: 本发明提供一种集成电路，其包括衬底，第一晶体管，第二晶体管和第三晶体管。 第一晶体管具有包括第一底部阻挡层，第一功函数金属层和第一金属层的第一金属栅极。 第二晶体管具有包括第二底部阻挡层，第二功函数金属层和第二金属层的第二金属栅极。 第三晶体管具有包括第三底部阻挡层，第三功函数金属层和第三金属层的第三金属栅极。 第一晶体管，第二晶体管和第三晶体管具有相同的导电类型。 第一底部阻挡层的氮浓度>第二底部阻挡层的氮浓度>第三底部阻挡层的氮浓度。

    RESISTIVE RANDOM ACCESS MEMORY AND MANUFACTURING METHOD THEREOF
    30.
    发明申请
    RESISTIVE RANDOM ACCESS MEMORY AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20230135098A1

    公开(公告)日：2023-05-04

    申请号：US17541280

    申请日：2021-12-03

    Applicant: United Microelectronics Corp.

    Inventor： Yi Yu Lin ,  Po Kai Hsu ,  Chun-Hao Wang ,  Yu-Ru Yang ,  Ju Chun Fan ,  Chung Yi Chiu

    IPC: H01L45/00 ,  H01L27/24

    Abstract: Provided are a resistive random access memory and a manufacturing method thereof. The resistive random access memory includes a substrate having a pillar protruding from a surface of the substrate, a gate surrounding a part of a side surface of the pillar, a gate dielectric layer, a first electrode, a second electrode, a variable resistance layer, a first doped region and a second doped region. The gate dielectric layer is disposed between the gate and the pillar. The first electrode is disposed on a top surface of the pillar. The second electrode is disposed on the first electrode. The variable resistance layer is disposed between the first electrode and the second electrode. The first doped region is disposed in the pillar below the gate and in a part of the substrate below the pillar. The second doped region is disposed in the pillar between the gate and the first electrode.

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