公开(公告)号：US20190103161A1

公开(公告)日：2019-04-04

申请号：US16126101

申请日：2018-09-10

Applicant: Unity Semiconductor Corporation

Inventor： Christophe Chevallier ,  Chang Hua Siau

IPC: G11C13/00 ,  G11C11/21

CPC classification number: G11C13/0033 ,  G11C11/21 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069

Abstract: Systems, integrated circuits, and methods to utilize access signals to facilitate memory operations in scaled arrays of memory elements are described. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements and line driver. The line driver can be configured to access a resistive memory element in the cross-point array.

公开(公告)号：US20190013070A1

公开(公告)日：2019-01-10

申请号：US16004705

申请日：2018-06-11

Applicant: Unity Semiconductor Corporation

Inventor： Christophe Chevallier ,  Chang Hua Siau

IPC: G11C13/00 ,  H03K19/0185 ,  H03K3/356 ,  G11C8/10 ,  G11C8/08

CPC classification number: G11C13/0023 ,  G11C8/08 ,  G11C8/10 ,  G11C13/0007 ,  G11C13/0028 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/77 ,  H03K3/356104 ,  H03K19/018521

Abstract: A system includes a cross-point memory array and a decoder circuit coupled to the cross-point memory array. The decoder circuit includes a predecoder having predecode logic to generate a control signal and a level shifter circuit to generate a voltage signal. The decoder circuit further includes a post-decoder coupled to the predecoder, the post-decoder including a first stage and a second stage coupled to the first stage, the control signal to control the first stage and the second stage to route the voltage signal through the first stage and the second stage to a selected conductive array line of a plurality of conductive array lines coupled to a memory array.

公开(公告)号：US10002646B2

公开(公告)日：2018-06-19

申请号：US14526894

申请日：2014-10-29

Applicant: UNITY SEMICONDUCTOR CORPORATION

Inventor： Chang Hua Siau ,  Christophe Chevallier ,  Darrell Rinerson ,  Seow Fong Lim ,  Sri Rama Namala

IPC: G11C5/02 ,  G11C8/00 ,  G11C11/00 ,  H01L21/82 ,  G11C13/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: G11C5/025 ,  G11C5/02 ,  G11C8/00 ,  G11C11/00 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/77 ,  H01L21/82 ,  H01L27/2481 ,  H01L45/16

Abstract: Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.

公开(公告)号：US09368200B2

公开(公告)日：2016-06-14

申请号：US14254209

申请日：2014-04-16

Applicant: Unity Semiconductor Corporation

Inventor： Bruce Lynn Bateman ,  Christophe Chevallier ,  Darrell Rinerson ,  Chang Hua Siau

IPC: G11C7/00 ,  G11C13/00 ,  G11C7/12 ,  G11C7/22

CPC classification number: G11C13/004 ,  G11C7/12 ,  G11C7/22 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0009 ,  G11C13/0011 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2013/0054 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/53 ,  G11C2213/71 ,  G11C2213/77

Abstract: A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured.

公开(公告)号：US20140334222A1

公开(公告)日：2014-11-13

申请号：US14254209

申请日：2014-04-16

Applicant: Unity Semiconductor Corporation

Inventor： Bruce Lynn Bateman ,  Christophe Chevallier ,  Darrell Rinerson ,  Chang Hua Siau

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C7/12 ,  G11C7/22 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0009 ,  G11C13/0011 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2013/0054 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/53 ,  G11C2213/71 ,  G11C2213/77

Abstract: A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured.

Abstract translation: 用于存储器的低读取当前体系结构。 允许交叉点存储器阵列的位线被选择的字线充电，直到确保存储器状态和参考电平之间的最小电压差。

公开(公告)号：US08854881B2

公开(公告)日：2014-10-07

申请号：US13858482

申请日：2013-04-08

Applicant: Unity Semiconductor Corporation

Inventor： Christophe Chevallier ,  Seow Fong Lim ,  Chang Hua Siau

IPC: G11C11/34 ,  G11C13/00 ,  G11C7/22 ,  G11C5/02 ,  G11C11/21 ,  B82Y30/00

CPC classification number: G11C7/22 ,  B82Y30/00 ,  G11C5/02 ,  G11C7/04 ,  G11C8/10 ,  G11C8/12 ,  G11C11/21 ,  G11C13/0021

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.

Abstract translation: 本发明的实施例一般涉及半导体和存储器技术，更具体地，涉及用于实现电路的系统，集成电路和方法，所述电路被配置为通过在存储器操作期间调整存取信号来补偿存储器层中的参数变化。 在一些实施例中，存储器单元基于第三维存储器技术。 在至少一些实施例中，集成电路包括多层存储器，包括半导体材料子层的层。 集成电路还包括被配置为生成访问信号以便于访问操作的访问信号发生器，以及被配置为调整多层存储器中的每层的访问信号的特征调整器。

公开(公告)号：US10354726B2

公开(公告)日：2019-07-16

申请号：US16126101

申请日：2018-09-10

Applicant: Unity Semiconductor Corporation

Inventor： Christophe Chevallier ,  Chang Hua Siau

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/21

Abstract: Systems, integrated circuits, and methods to utilize access signals to facilitate memory operations in scaled arrays of memory elements are described. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements and line driver. The line driver can be configured to access a resistive memory element in the cross-point array.

公开(公告)号：US20180182454A1

公开(公告)日：2018-06-28

申请号：US15823270

申请日：2017-11-27

Applicant: Unity Semiconductor Corporation

Inventor： Christophe Chevallier ,  Robert Norman

IPC: G11C13/00

Abstract: Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power. Over a period of time, logic values indicative of the stored data may drift such that if the logic values are not restored, the stored data may become corrupted. At least a portion of each memory may have data rewritten or restored by circuitry electrically coupled with the memory. Other circuitry may be used to determine a schedule for performing restore operations to the memory and the restore operations may be triggered by an internal or an external signal or event. The circuitry may be positioned in a logic layer and the memory may be fabricated over the logic layer.

公开(公告)号：US20180096726A1

公开(公告)日：2018-04-05

申请号：US15706342

申请日：2017-09-15

Applicant: Unity Semiconductor Corporation

Inventor： Christophe Chevallier ,  Chang Hua Siau

IPC: G11C13/00

CPC classification number: G11C13/0033 ,  G11C11/21 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069

Abstract: Systems, integrated circuits, and methods to utilize access signals to facilitate memory operations in scaled arrays of memory elements are described. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements and line driver. The line driver can be configured to access a resistive memory element in the cross-point array.

公开(公告)号：US09837149B2

公开(公告)日：2017-12-05

申请号：US15181009

申请日：2016-06-13

Applicant: UNITY SEMICONDUCTOR CORPORATION

Inventor： Bruce Lynn Bateman ,  Christophe Chevallier ,  Darrell Rinerson ,  Chang Hua Siau

IPC: G11C17/00 ,  G11C13/00 ,  G11C7/12 ,  G11C7/22

CPC classification number: G11C13/004 ,  G11C7/12 ,  G11C7/22 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0009 ,  G11C13/0011 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2013/0054 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/53 ,  G11C2213/71 ,  G11C2213/77

Abstract: A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured.