公开(公告)号：US20160077078A1

公开(公告)日：2016-03-17

申请号：US14659432

申请日：2015-03-16

Applicant: Quantapore, Inc.

Inventor： Martin HUBER ,  Bason E. CLANCY ,  Adam R. HALL

IPC: G01N33/487 ,  B81B7/02 ,  B81C1/00

CPC classification number: G01N33/48721 ,  B81B7/02 ,  B81B2201/0214 ,  B81B2201/047 ,  B81B2203/0353 ,  B81C1/00206 ,  C12Q1/6818 ,  C12Q1/6869 ,  C12Q2525/101 ,  C12Q2565/101 ,  C12Q2565/631

Abstract: Methods for fabricating materials useful for optical detection in microfluidic and nanofluidic devices, such as those used in nanopore-based nucleic acid sequencing are described herein. In certain variations, a method of reducing background fluorescence in a MEMS material may include the step of treating a surface of the MEMS material with a low energy ion beam.

Abstract translation: 本文描述了用于微流体和纳流体装置中用于光学检测的材料的方法，例如在纳米孔核酸测序中使用的那些。 在某些变型中，降低MEMS材料中背景荧光的方法可包括用低能量离子束处理MEMS材料的表面的步骤。

公开(公告)号：US09285363B2

公开(公告)日：2016-03-15

申请号：US13319989

申请日：2010-05-10

Applicant: F. Raymond Salemme ,  Patricia C. Weber

Inventor： F. Raymond Salemme ,  Patricia C. Weber

IPC: B82Y5/00 ,  G01N33/543 ,  B81C1/00 ,  B82Y30/00

CPC classification number: G01N33/54386 ,  B01J2219/00605 ,  B01J2219/00612 ,  B01J2219/00617 ,  B01J2219/00626 ,  B01J2219/0063 ,  B01J2219/00637 ,  B01J2219/00725 ,  B81B2201/0214 ,  B81C1/00206 ,  B82Y30/00

Abstract: A method of assembling a protein nanostructure on a surface including selectively patterning a surface with a fixation site, bringing a protein node into contact with the surface, and allowing the protein node to bond with the fixation site, so that the position and/or orientation of the protein node is constrained, and compositions.

Abstract translation: 一种在表面上组装蛋白质纳米结构的方法，包括用固定部位选择性地图案化表面，使蛋白质节点与表面接触，并使蛋白质节点与固定部位结合，使得位置和/或取向 的蛋白质节点被约束，并且组成。

公开(公告)号：US09267915B2

公开(公告)日：2016-02-23

申请号：US14594913

申请日：2015-01-12

Applicant: Analog Devices, Inc.

Inventor： Alan J. O'Donnell ,  Santiago Iriarte ,  Mark J. Murphy ,  Colin G. Lyden ,  Gary Casey ,  Eoin Edward English

IPC: G01N27/414 ,  H01L31/06 ,  H01L25/16 ,  H01L23/48 ,  B81B7/00 ,  G01N27/26 ,  H01L27/14 ,  H01L27/15 ,  H01L49/02 ,  H01L31/0392 ,  H01F17/00 ,  H01L21/82 ,  H01L27/06 ,  H01L23/00 ,  H01F17/04 ,  H02S40/38 ,  H02S10/10 ,  H01L31/053 ,  H01L35/00 ,  H01L35/28 ,  H01L23/58 ,  G01N27/22 ,  H01L31/052 ,  H01L23/367 ,  H01L23/38 ,  H01L23/473

CPC classification number: G01N27/226 ,  B81B7/00 ,  B81B7/007 ,  B81B2201/0214 ,  G01N27/26 ,  G01N27/4148 ,  H01F17/00 ,  H01F17/04 ,  H01L21/82 ,  H01L23/3677 ,  H01L23/38 ,  H01L23/473 ,  H01L23/481 ,  H01L23/58 ,  H01L24/05 ,  H01L24/13 ,  H01L24/48 ,  H01L24/94 ,  H01L25/16 ,  H01L25/167 ,  H01L27/0694 ,  H01L27/14 ,  H01L27/15 ,  H01L28/00 ,  H01L28/10 ,  H01L28/20 ,  H01L28/60 ,  H01L28/82 ,  H01L28/86 ,  H01L28/90 ,  H01L31/0392 ,  H01L31/0525 ,  H01L31/0547 ,  H01L31/056 ,  H01L31/06 ,  H01L35/00 ,  H01L35/28 ,  H01L35/30 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/0556 ,  H01L2224/0557 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48265 ,  H01L2225/06531 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/16195 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H02S10/10 ,  H02S40/38 ,  Y02E10/50 ,  Y02E10/52 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05552 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.

公开(公告)号：US20160023889A1

公开(公告)日：2016-01-28

申请号：US14532675

申请日：2014-11-04

Applicant: Silicon Laboratories Inc.

Inventor： Emmanuel P. Quevy ,  Jeremy R. Hui ,  Carrie Wing-Zin Low

IPC: B81B7/00 ,  B81C1/00 ,  B81B3/00

CPC classification number: B81C1/00246 ,  B81B3/0021 ,  B81B7/007 ,  B81B7/0077 ,  B81B7/008 ,  B81B2201/0214 ,  B81B2201/0235 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81C1/00158 ,  B81C1/00269 ,  B81C1/00285 ,  B81C1/00333 ,  B81C1/0038 ,  B81C2201/0105 ,  B81C2201/056 ,  B81C2203/0118 ,  B81C2203/0136 ,  B81C2203/0172 ,  B81C2203/019 ,  B81C2203/0735 ,  G01N27/223 ,  G01N27/227

Abstract: Membrane transducer structures and thin-film encapsulation methods for manufacturing the same are provided. In one example, the thin film encapsulation methods may be implemented to co-integrate processes for thin-film encapsulation and formation of microelectronic devices and microelectromechanical systems (MEMS) that include the membrane transducers.

Abstract translation: 提供了用于制造薄膜换能器结构和薄膜封装方法。 在一个示例中，可以实现薄膜封装方法以共同整合用于薄膜封装和形成微电子器件的工艺和包括膜换能器的微机电系统（MEMS）。

公开(公告)号：US09168717B2

公开(公告)日：2015-10-27

申请号：US14024165

申请日：2013-09-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Yann Astier ,  Jingwei Bai ,  Satyavolu Papa Rao ,  Kathleen Reuter ,  Joshua T. Smith

IPC: B32B3/24 ,  B81B1/00 ,  B82Y99/00 ,  B32B3/26 ,  G01N27/414 ,  G01N33/487 ,  B82Y5/00 ,  B82Y15/00 ,  B82Y40/00

CPC classification number: B32B3/266 ,  B32B2250/03 ,  B32B2307/204 ,  B32B2457/00 ,  B81B1/004 ,  B81B2201/0214 ,  B81B2203/0127 ,  B81B2203/0353 ,  B81C1/00087 ,  G01N27/4145 ,  G01N27/4146 ,  G01N33/48721 ,  Y10T428/24322

Abstract: Solid state nanopore devices for nanopore applications and methods of manufacture are disclosed herein. The method includes forming a membrane layer on an underlying substrate. The method further includes forming a hole in the membrane layer. The method further comprises plugging the hole with a sacrificial material. The method further includes forming a membrane over the sacrificial material. The method further includes removing the sacrificial material within the hole and portions of the underlying substrate. The method further includes drilling an opening in the membrane, aligned with the hole.

Abstract translation: 本文公开了用于纳米孔应用的固态纳米孔装置和制造方法。 该方法包括在下面的基底上形成膜层。 该方法还包括在膜层中形成孔。 该方法还包括用牺牲材料堵塞孔。 该方法还包括在牺牲材料上形成膜。 该方法还包括去除孔内的牺牲材料和底层基底的部分。 所述方法还包括在所述膜中钻出与所述孔对准的开口。

公开(公告)号：US20150241385A1

公开(公告)日：2015-08-27

申请号：US14706495

申请日：2015-05-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Yann ASTIER ,  Jingwei BAI ,  Satyavolu PAPA RAO ,  Kathleen REUTER ,  Joshua T. SMITH

IPC: G01N27/414

CPC classification number: B32B3/266 ,  B32B2250/03 ,  B32B2307/204 ,  B32B2457/00 ,  B81B1/004 ,  B81B2201/0214 ,  B81B2203/0127 ,  B81B2203/0353 ,  B81C1/00087 ,  G01N27/4145 ,  G01N27/4146 ,  G01N33/48721 ,  Y10T428/24322

Abstract: Solid state nanopore devices for nanopore applications and methods of manufacture are disclosed herein. The method includes forming a membrane layer on an underlying substrate. The method further includes forming a hole in the membrane layer. The method further comprises plugging the hole with a sacrificial material. The method further includes forming a membrane over the sacrificial material. The method further includes removing the sacrificial material within the hole and portions of the underlying substrate. The method further includes drilling an opening in the membrane, aligned with the hole.

Abstract translation: 本文公开了用于纳米孔应用的固态纳米孔装置和制造方法。 该方法包括在下面的基底上形成膜层。 该方法还包括在膜层中形成孔。 该方法还包括用牺牲材料堵塞孔。 该方法还包括在牺牲材料上形成膜。 该方法还包括去除孔内的牺牲材料和下面的基底的部分。 所述方法还包括在所述膜中钻出与所述孔对准的开口。

公开(公告)号：US20150210534A1

公开(公告)日：2015-07-30

申请号：US14422654

申请日：2013-08-20

Applicant: CORNELL UNIVERSITY

Inventor： Robert MacCurdy ,  Hod Lipson

IPC: B81B3/00 ,  B01L3/00 ,  B81B5/00

CPC classification number: B81B3/0021 ,  B01D61/427 ,  B01L3/502746 ,  B81B5/00 ,  B81B2201/0214 ,  B81B2201/058 ,  B81B2203/04 ,  B81B2203/06 ,  F25B41/02

Abstract: The invention exploits a widely used device in micro-fluidics, the electro-osmotic pump (EOP), to create very low energy micro-scale and macro-scale mechanical actuators. The EOP uses electrical fields to move naturally occurring charged particles (ions) through a fluid medium. As the ions move in response to the applied field, they drag the (non-charged) fluid along, establishing bulk flow. When confined to a narrow chamber, a pressure gradient can be established. The combination of pressure gradient and flow performs mechanical work. With the use of electro-osmotic pumps, the invention enables actuators to be constructed in a variety of embodiments, including for example, a sheet structure, a piston structure, and a cellular structure to name a few.

Abstract translation: 本发明利用了广泛使用的微流体学设备，即电渗泵（EOP），以创建极低能量的微尺度和宏观尺度的机械致动器。 EOP使用电场来移动天然存在的带电粒子（离子）通过流体介质。 当离子响应于所施加的场移动时，它们沿着沿着（非带电）的流体拖动，建立大量流动。 当限制在狭窄的室中时，可以建立压力梯度。 压力梯度和流量的组合执行机械作业。 通过使用电渗透泵，本发明使致动器能够以各种实施例构造，例如，薄片结构，活塞结构和细胞结构等等。

公开(公告)号：US08968673B2

公开(公告)日：2015-03-03

申请号：US13805491

申请日：2011-06-29

Applicant: Vincent Agache ,  Antoine Hoang ,  Françoise Vinet

Inventor： Vincent Agache ,  Antoine Hoang ,  Françoise Vinet

IPC: G01N33/00 ,  G03F7/24 ,  B81C1/00 ,  F04B19/00

CPC classification number: G03F7/24 ,  B81B2201/0214 ,  B81B2201/058 ,  B81B2201/06 ,  B81C1/00206 ,  B81C2201/0154 ,  F04B19/006

Abstract: The present invention relates to a method for functionalizing fluid lines (1b) in a micromechanical device, the walls of which include an opaque layer. For this purpose, the invention provides a method for functionalizing a micromechanical device provided with a fluid line including a peripheral wall (5) having a surface (2) outside the line and an inner surface (3) defining a space (1b) in which a fluid can circulate, the peripheral wall at least partially including a silicon layer (5a). The method includes the following steps: a) providing a device, the peripheral wall (5) of which at least partially includes a silicon layer (5a) having, at least locally, a thickness (e) of more than 100 nm and less than 200 nm, advantageously of 160 to 180 nm; c) silanizing at least the inner surface of the fluid line; d) the localized, selective photo-deprotection on at least the inner surface of the silanized device by exposing the peripheral wall (5) at the point at which said wall has a thickness (e) of more than 100 nm and less than 200 nm, advantageously of 160 to 180 nm.

Abstract translation: 本发明涉及一种在微机械装置中功能化流体管线（1b）的方法，该方法的壁包括不透明层。 为此，本发明提供了一种功能化微机械装置的方法，该微机械装置具有流体管线，该流体管线包括在管线外部具有表面（2）的周壁（5）和限定空间（1b）的内表面（3） 流体可以循环，周壁至少部分地包括硅层（5a）。 该方法包括以下步骤：a）提供一种器件，其外围壁（5）至少部分地包括硅层（5a），该硅层至少局部地具有大于100nm的厚度（e）并且小于 200nm，有利地为160〜180nm; c）至少使流体管线的内表面硅烷化; d）通过在所述壁的厚度（e）大于100nm且小于200nm的点处暴露外围壁（5），至少在硅烷化装置的内表面上进行局部选择性光 - 去保护 ，有利地为160至180nm。

公开(公告)号：US20150056732A1

公开(公告)日：2015-02-26

申请号：US14010158

申请日：2013-08-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Yann ASTIER ,  Jingwei BAI ,  Satyavolu PAPA RAO ,  Kathleen REUTER ,  Joshua T. SMITH

IPC: G01N27/414

CPC classification number: B32B3/266 ,  B32B2250/03 ,  B32B2307/204 ,  B32B2457/00 ,  B81B1/004 ,  B81B2201/0214 ,  B81B2203/0127 ,  B81B2203/0353 ,  B81C1/00087 ,  G01N27/4145 ,  G01N27/4146 ,  G01N33/48721 ,  Y10T428/24322

Abstract: Solid state nanopore devices for nanopore applications and methods of manufacture are disclosed herein. The method includes forming a membrane layer on an underlying substrate. The method further includes forming a hole in the membrane layer. The method further comprises plugging the hole with a sacrificial material. The method further includes forming a membrane over the sacrificial material. The method further includes removing the sacrificial material within the hole and portions of the underlying substrate. The method further includes drilling an opening in the membrane, aligned with the hole.

公开(公告)号：US08866239B2

公开(公告)日：2014-10-21

申请号：US13289063

申请日：2011-11-04

Applicant: Marcus Van Dal ,  Aurelie Humbert ,  Matthias Merz ,  Youri Victorovitch Ponomarev

Inventor： Marcus Van Dal ,  Aurelie Humbert ,  Matthias Merz ,  Youri Victorovitch Ponomarev

IPC: H01L27/14 ,  H01L29/66 ,  H01L23/34

CPC classification number: B81B7/0012 ,  B81B2201/0214 ,  B81B2207/015 ,  B81C2201/016

Abstract: A method of manufacturing an integrated circuit having a substrate comprising a plurality of components and a metallization stack over the components, the metallization stack comprising a first sensing element and a second sensing element adjacent to the first sensing element.

Abstract translation: 一种制造集成电路的方法，所述集成电路具有包括多个部件的基板和在所述部件上的金属化叠层，所述金属化堆叠包括第一感测元件和与所述第一感测元件相邻的第二感测元件。