Patent search cpc:"H05K2201/10159" Page 3

21.

发明授权
Storage devices and methods of operating storage devices 有权

公开(公告)号：US11825596B2

公开(公告)日：2023-11-21

申请号：US17167209

申请日：2021-02-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiwoon Park

IPC: H05K1/00 , H05K1/02 , H03H7/06 , H05K1/11

CPC classification number: H05K1/0233 , H03H7/06 , H05K1/112 , H05K2201/094 , H05K2201/10159

Abstract: A storage device is provided. The storage device includes nonvolatile memory devices provided on a printed circuit board (PCB), a connector, a storage controller and at least one first passive filter. The connector is provided in the PCB and includes connection terminals. The storage controller is provided on the PCB, communicates with an external host through the connection terminals and controls the nonvolatile memory devices. The at least one first passive filter is provided in the PCB, is connected between the connector and the storage controller, and performs an equalization on either a signal provided to the storage controller or a signal provided from the storage controller.

22.

发明授权
Flexible printed circuit finger layout for low crosstalk 有权

公开(公告)号：US11818834B2

公开(公告)日：2023-11-14

申请号：US17356155

申请日：2021-06-23

Applicant: Western Digital Technologies, Inc.

Inventor： Masahiro Kishimoto , John Contreras , Kazuhiro Nagaoka , Satoshi Nakamura

IPC: H05K1/02

CPC classification number: H05K1/0228 , H05K1/028 , H05K1/0298 , H05K2201/10159

Abstract: A flexible printed circuit (FPC) for a hard disk drive includes a plurality of electrical traces, whereby aggressor traces are isolated from victim traces to avoid crosstalk that could degrade signals. Aggressor traces may be positioned together at one of the edges of each of the top wiring layer and the bottom wiring layer, physically isolated from victim traces. Aggressor traces may be grouped together at either the top wiring layer or the bottom wiring layer, with the victim traces positioned on the layer opposing the aggressor traces. With aggressor and victim traces routed on the same wiring layer, aggressor traces may be routed away from the victim traces with multi-layer routing, by way of vias.

23.

发明授权
Memory card 有权

公开(公告)号：US11785732B2

公开(公告)日：2023-10-10

申请号：US17227043

申请日：2021-04-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngwoo Park

IPC: H05K5/02 , H01L25/18 , H05K1/02 , H05K1/18

CPC classification number: H05K5/026 , H01L25/18 , H05K1/0271 , H05K1/18 , H05K2201/09027 , H05K2201/10159

Abstract: A memory card includes a case and an integrated circuit package disposed in the case. The case includes a first case edge, a second case edge connected to the first case edge, a third case edge connected to the second case edge, a fourth case edge connected to the third case edge and the first case edge, and a first recessed groove formed in the second case edge, the first recessed groove being spaced apart from the first case edge and inwardly recessed. The integrated circuit package is disposed in an upper portion of the case between the first case edge and a first horizontal line that extends in a direction from a top end of the first recessed groove in the second case edge to the fourth case edge.

24.

发明授权
Module board and memory module including the same 有权

公开(公告)号：US11785710B2

公开(公告)日：2023-10-10

申请号：US17947397

申请日：2022-09-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonseop Lee , Hwanwook Park , Jeonghoon Baek , Dohyung Kim , Seunghee Mun , Dongyoon Seo , Jinoh Ahn

IPC: G11C5/04 , H05K1/02 , H01L25/11 , H01L25/065 , G11C5/06 , G11C8/18 , G06F13/40

CPC classification number: H05K1/0246 , G06F13/4086 , G11C5/04 , G11C5/063 , G11C8/18 , H01L25/0657 , H01L25/112 , H05K1/025 , H05K2201/10159

Abstract: A module board and a memory module are provided. The module board includes a first branch line for connecting a clock signal terminal disposed on at least one surface to a first branch point; a first signal line for connecting the first branch point to a first module clock signal terminal; a second signal line for connecting the first module clock signal terminal to the kth module clock signal terminal and a first termination resistance terminal; a third signal line for connecting the first branch point to a (k+1)th module clock signal terminal; and a fourth signal line for connecting the (k+1)th module clock signal terminal to a 2kth module clock signal terminal and the second termination resistance terminal, wherein a length of the third signal line is greater than a sum of a length of the first signal line and a length of the second signal line.

25.

发明授权
Structure of memory module and modification method of memory module 有权

公开(公告)号：US11778740B2

公开(公告)日：2023-10-03

申请号：US17475974

申请日：2021-09-15

Applicant: Shih-Hsiung Lien

Inventor： Shih-Hsiung Lien

IPC: H05K1/11 , H05K1/02

CPC classification number: H05K1/111 , H05K1/0203 , H05K2201/10159

Abstract: An improved memory module structure includes a printed circuit board, memory units disposed on the printed circuit board, and a connection interface disposed on the printed circuit board for connection with an electronic device. The printed circuit board includes a solder pad zone having solder pads electrically connected with the memory units and the connection interface. A conduction element is combined with the solder pad zone or at least one conductor line electrically connected, in the form of bridge connection, the solder pads, in order to have the solder pads electrically connected. A memory module modification method is also provided, including removing a register from an existing dual inline memory module to expose a solder pad zone, and disposing of a conduction element or arranging a conductor line to have the memory units and the connection interface of electrically connected to thereby form an improved memory module structure.

26.

发明公开
SEMICONDUCTOR MEMORY SYSTEM 审中-公开

公开(公告)号：US20230307433A1

公开(公告)日：2023-09-28

申请号：US18203693

申请日：2023-05-31

Applicant: Kioxia Corporation

Inventor： Hayato MASUBUCHI , Naoki KIMURA , Manabu MATSUMOTO , Toyota MORIMOTO

IPC: H01L25/18 , H05K1/02 , H05K3/30 , H10B69/00 , H01L23/498 , G11C5/02 , H01L23/31 , H01L23/552 , H01L23/00 , H01L25/065 , H05K1/18 , H01L23/528 , H01L25/00

CPC classification number: H01L25/18 , H05K1/0225 , H05K1/0271 , H05K1/0298 , H05K3/305 , H10B69/00 , H01L23/49822 , G11C5/02 , H01L23/3142 , H01L23/49838 , H01L23/552 , H01L23/562 , H01L25/0655 , H05K1/181 , H01L23/5286 , H01L25/50 , H01L23/3121 , H05K2201/09136 , H05K2201/09681 , H05K2201/10159 , H01L2924/0002 , Y02P70/50

Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.

27.

发明公开
SEMICONDUCTOR STORAGE DEVICE 审中-公开

公开(公告)号：US20230284390A1

公开(公告)日：2023-09-07

申请号：US18079514

申请日：2022-12-12

Applicant: Kioxia Corporation

Inventor： Kazuya NAGASAWA , Norihiro ISHII , Kazuhiro NOJIMA , Tamotsu FUJIMAKI

IPC: H05K1/18

CPC classification number: H05K1/182 , H05K2201/10159

Abstract: A semiconductor storage device according to an embodiment includes a board, an electronic component, and a holder. The board has a first surface. The electronic component includes a component main body and a first lead. The component main body is at a position out of the board in a direction parallel to the first surface. The first lead protrudes from the component main body toward the board. The holder is on the board. The holder holds the first lead.

28.

发明公开
STORAGE DEVICE INCLUDING CONFIGURABLE PRINTED CIRCUIT BOARD 审中-公开

公开(公告)号：US20230284378A1

公开(公告)日：2023-09-07

申请号：US18103175

申请日：2023-01-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sun-Ki YUN , Hwi-Jong Yoo , Jeonggi Yoon

IPC: H05K1/02 , H05K1/16 , G06F3/06 , G06F13/10

CPC classification number: H05K1/0286 , H05K1/0296 , H05K1/167 , G06F3/0679 , G06F13/10 , H05K2201/10159 , H05K2201/10659 , G06F2213/0026

Abstract: A storage device includes a printed circuit board including a controller site, a first memory site, a second memory site, first conductive lines connected with the controller site, second conductive lines connected with the first memory site, and third conductive lines connected with the second memory site, a controller package provided on the controller site, a first nonvolatile memory package provided on the first memory site, a second nonvolatile memory package provided on the second memory site, and at least one resistor connecting at least one conductive line of the first conductive lines with at least one conductive line of the second conductive lines.

29.

发明授权
Memory device with split power supply capability 有权

公开(公告)号：US11735232B2

公开(公告)日：2023-08-22

申请号：US17202326

申请日：2021-03-15

Applicant: MONTAGE TECHNOLOGY CO., LTD.

Inventor： Christopher Cox

IPC: G11C5/04 , G11C5/14 , H05K1/18

CPC classification number: G11C5/147 , G11C5/04 , H05K1/181 , H05K2201/10159

Abstract: A memory device includes a printed circuit board having a plurality of conductive layers; memory chips mounted over the printed circuit board, wherein the memory chips comprise at least a first number of memory chips and a second number of memory chips; a first power module mounted over the printed circuit board and for providing a first set of power supplies to the first number of memory chips through the plurality of conductive layers; and a second power module mounted over the printed circuit board and for providing a second set of power supplies to the second number of memory chips through the plurality of conductive layers.