Abstract:
An electronic component having an electrode structure to increase an allowance positional deviation in a mounting process as well as a method and a structure for mounting a semiconductor device are provided. The semiconductor device includes, on electrodes, connection materials connecting the semiconductor device and a substrate. The connection materials include a composite connection material formed of a core and a conductor covering the core, the core having an a low modulus of elasticity at room temperature smaller than that of the conductor at room temperature, and a single-layer connection material formed of a conductor.
Abstract:
Techniques for utilizing a bonding agent that allows a solder reflow process to occur at a lower reflow temperature. One area of use includes semiconductor device manufacturing processes. The bonding agent is placed between a solder ball and a contact surface. The bonding agent has a melting temperature that is lower than that of the solder ball. Reflow is then performed at a relative low temperature that is high enough for reflowing the bonding agent, yet at the same time, lower than what would be necessary to reflow the solder material. Since, the electrical system is not subjected to the high temperatures necessary for reflowing the solder material, the electronic system experiences less high-temperature related damage.
Abstract:
A semiconductor device in chip format having a chip which has at least one first insulating layer and electrical connection pads free of the insulating layer is described. On the first insulating layer, interconnects run from the electrical connection pads to base regions of external connection elements. A further applied insulating layer is provided with openings leading from the outside to the base regions of the external connection elements. In the openings there is a conductive adhesive, onto which small balls which are metallic at least on the outside are placed. The semiconductor element can also contain a solder paste instead of a conductive adhesive in the openings, and metallized small plastic balls are placed onto the solder paste. The invention furthermore relates to methods for producing the semiconductor device described.
Abstract:
A ball grid array package includes a substrate with a top and bottom surface. A circuit component is located on the bottom surface. The circuit component has a pair of ends. A pair of conductors are located on the bottom surface. The conductors are connected to the ends of the circuit component. A conductive epoxy covers a portion of the conductors and a portion of the bottom surface. The conductive epoxy is in electrical contact with the conductors. A ball is connected to the conductive epoxy. The conductive epoxy provides an electrical connection between the conductor and the ball. The ball is preferably copper and is subsequently coated to prevent corrosion. Other embodiments of the invention are shown in which the balls are omitted and in which the conductive epoxy is used to fill vias in a substrate.
Abstract:
A microelectronic assembly includes a first microelectronic element having a contact bearing face and one or more contacts provided at the contact bearing face and a second microelectronic element juxtaposed with the first microelectronic element, the second microelectronic element having a first surface including one or more conductive pads. The microelectronic assembly also includes one or more conductive masses electrically interconnecting the contacts of the first microelectronic element and the conductive pads of the second microelectronic element, whereby each the conductive mass includes a first region comprising a first fusible material transformable from a solid to a liquid at a first melting temperature and a second region comprising a second fusible material transformable from a solid to a liquid at a second melting temperature that is less than the first melting temperature.
Abstract:
Apparatus and methods providing for interconnecting a SMT component interconnect to a via-in-pad (VIP) interconnect is presented. In one embodiment in accordance with the invention, a first reflowable electrically conductive interconnect material is deposited on the VIP bond pad. A sphere comprising an electrically conductive material having a higher melt temperature than the reflow temperature of the first interconnect material is deposited on the first interconnect material. A first reflow process is performed to interconnect the sphere and the VIP bond pad while the sphere remains solid. A second electrically conductive interconnect material having a reflow temperature lower than the melt temperature of the sphere is deposited on the component interconnect and a second reflow process is performed to interconnect the sphere to the component interconnect while the sphere remains solid, effectively preventing the second interconnect material from migrating into the plated though hole.
Abstract:
An electrical structure, and associated method of fabrication, for reducing thermally induced strain in a structure that couples a first conductive body of a first substrate to a second conductive body of a second substrate (e.g., a chip to a chip carrier; a chip carrier to a circuit card). The melting point of the first conductive body exceeds the melting point of the second conductive body. The second conductive body may include eutectic lead-tin alloy, while the first conductive body may include non-eutectic lead-tin alloy. A portion of the first conductive body is coated with, or volumetrically surrounded by, a material that is nonsolderable and nonconductive. The first and second conductive bodies are coupled mechanically and electrically by surface adhesion at an uncoated portion of the first conductive body, by application of a temperature that lies between the melting points of the first and second conductive bodies.
Abstract:
A solder ball array type package structure is able to control collapse. The package includes a substrate, a carrier, a plurality of dies, a molding compound and a plurality of solder balls. The substrate has at least one active surface. Pads are located on the first surface of the substrate. The carrier has at least an active surface and a back surface opposite the active surface. A plurality of dies are located on the back surface and the active surface of the carrier. The dies arranged on the active surface are electrically connected to the carrier by flip chip technology. A molding compound encapsulates on the back surface of the carrier to cover the dies on the back surface of the carrier. Solder balls having a base material are provided on the active surface of the carrier in array. At least three solder balls coated with the base material having a high melting-temperature core are further provided in the periphery of the array. The carrier is arranged such that the active surface faces the first surface of the substrate to allow each solder ball correspond to the one of the pads, respectively.
Abstract:
In one embodiment of the invention, a stacking element includes a printed circuit board (PCB) and a plurality of solder bumps. The PCB has a top side and a bottom side. The top side is attached to first pins of a first device. The plurality of solder bumps are on the bottom side and attached to upper areas of second pins of a second device to provide electrical connections between the first pins and the second pins.
Abstract:
The invention includes an interposer, BGA connector, or other connection device that provides electrical contact with a ball grid array connector. The inventive interposer includes a housing with contacts. The contacts have a first end and a second end. The interposer also includes a first body and a second body of reflowable, electrically conductive material disposed on the first end of at least one of the contacts. The first body and the second body provide an electrical contact between the interposer and a single body of reflowable, electrically conductive material of the ball gid array connector.