公开(公告)号：US20240162190A1

公开(公告)日：2024-05-16

申请号：US18523665

申请日：2023-11-29

Applicant: Adeia Semiconductor Inc.

Inventor： Javier A. DeLaCruz ,  Belgacem Haba ,  Cyprian Emeka Uzoh ,  Rajesh Katkar ,  Ilyas Mohammed

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L24/08 ,  H01L24/11 ,  H01L2224/08146 ,  H01L2224/11464 ,  H01L2224/119 ,  H01L2224/13005 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06555

Abstract: An integrated circuit and a method for designing an IC wherein the base or host chip is bonded to smaller chiplets via DBI technology. The bonding of chip to chiplet creates an uneven or multi-level surface of the overall chip requiring a releveling for future bonding. The uneven surface is built up with plating of bumps and subsequently releveled with various methods including planarization.

公开(公告)号：US11916076B2

公开(公告)日：2024-02-27

申请号：US16915140

申请日：2020-06-29

Applicant: Adeia Semiconductor Inc.

Inventor： Javier A. Delacruz ,  Don Draper ,  Jung Ko ,  Steven L. Teig

IPC: H01L25/065 ,  H01L25/00 ,  H01L27/118

CPC classification number: H01L27/11807 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2027/11838 ,  H01L2027/11875 ,  H01L2027/11879 ,  H01L2027/11881

Abstract: The present disclosure provides chip architectures for FPGAs and other routing implementations that provide for increased memory with high bandwidth, in a reduced size, accessible with reduced latency. Such architectures include a first layer in advanced node and a second layer in legacy node. The first layer includes an active die, active circuitry, and a configurable memory, and the second layer includes a passive die with wiring. The second layer is bonded to the first layer such that the wiring of the second layer interconnects with the active circuitry of the first layer and extends an amount of wiring possible in the first layer.

公开(公告)号：US11914148B2

公开(公告)日：2024-02-27

申请号：US16124617

申请日：2018-09-07

Applicant: ADEIA SEMICONDUCTOR INC.

Inventor： Ilyas Mohammed ,  Rajesh Katkar ,  Belgacem Haba

IPC: G02B27/14 ,  G02B27/01 ,  F21V8/00

CPC classification number: G02B27/0172 ,  G02B6/0035 ,  G02B6/0076 ,  G02B27/144 ,  G02B2027/0178

Abstract: An optical apparatus is provided comprising: first and second optical waveguides disposed in a substrate such that light reflected by a beam splitting optical element of the first waveguide passes between beam splitting elements of the second waveguide.