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    Stacked IC structure with orthogonal interconnect layers
    2.
    发明授权
    Stacked IC structure with orthogonal interconnect layers 有权

    公开(公告)号：US12218059B2

    公开(公告)日：2025-02-04

    申请号：US18399485

    申请日：2023-12-28

    Applicant: Adeia Semiconductor Inc.

    Inventor： Ilyas Mohammed ,  Steven L. Teig ,  Javier A. DeLaCruz

    IPC: H01L23/528 ,  H01L21/822 ,  H01L23/00 ,  H01L23/50 ,  H01L23/522 ,  H01L25/065 ,  H01L27/06

    Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die.

    TRANSISTOR LEVEL INTERCONNECTION METHODOLOGIES UTILIZING 3D INTERCONNECTS
    6.
    发明申请
    TRANSISTOR LEVEL INTERCONNECTION METHODOLOGIES UTILIZING 3D INTERCONNECTS 有权

    公开(公告)号：US20230138732A1

    公开(公告)日：2023-05-04

    申请号：US18147651

    申请日：2022-12-28

    Applicant: Adeia Semiconductor Inc.

    Inventor： Javier A. DeLaCruz ,  David Edward Fisch

    IPC: H01L29/417 ,  H01L29/08 ,  H01L29/06 ,  H01L23/00 ,  H01L23/538 ,  H01L21/762 ,  H01L29/66 ,  H01L21/02

    Abstract: A microelectronic unit may include an epitaxial silicon layer having a source and a drain, a buried oxide layer beneath the epitaxial silicon layer, an ohmic contact extending through the buried oxide layer, a dielectric layer beneath the buried oxide layer, and a conductive element extending through the dielectric layer. The source and the drain may be doped portions of the epitaxial silicon layer. The ohmic contact may be coupled to a lower surface of one of the source or the drain. The conductive element may be coupled to a lower surface of the ohmic contact. A portion of the conductive element may be exposed at the second dielectric surface of the dielectric layer. The second dielectric surface may be directly bonded to an external component to form a microelectronic assembly.

    Transistor level interconnection methodologies utilizing 3D interconnects
    7.
    发明授权
    Transistor level interconnection methodologies utilizing 3D interconnects 有权

    公开(公告)号：US12272730B2

    公开(公告)日：2025-04-08

    申请号：US18147651

    申请日：2022-12-28

    Applicant: Adeia Semiconductor Inc.

    Inventor： Javier A. DeLaCruz ,  David Edward Fisch

    IPC: H01L29/66 ,  H01L21/02 ,  H01L21/762 ,  H01L23/00 ,  H01L23/538 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417

    Abstract: A microelectronic unit may include an epitaxial silicon layer having a source and a drain, a buried oxide layer beneath the epitaxial silicon layer, an ohmic contact extending through the buried oxide layer, a dielectric layer beneath the buried oxide layer, and a conductive element extending through the dielectric layer. The source and the drain may be doped portions of the epitaxial silicon layer. The ohmic contact may be coupled to a lower surface of one of the source or the drain. The conductive element may be coupled to a lower surface of the ohmic contact. A portion of the conductive element may be exposed at the second dielectric surface of the dielectric layer. The second dielectric surface may be directly bonded to an external component to form a microelectronic assembly.

    Three dimensional circuit implementing machine trained network
    8.
    发明授权
    Three dimensional circuit implementing machine trained network 有权

    公开(公告)号：US12248869B2

    公开(公告)日：2025-03-11

    申请号：US18469910

    申请日：2023-09-19

    Applicant: Adeia Semiconductor Inc.

    Inventor： Steven L. Teig ,  Kenneth Duong

    IPC: G06N3/065 ,  G06F11/14 ,  G06F11/20 ,  G06N3/04 ,  G06N3/048 ,  G06N3/063 ,  G06N3/08 ,  G06N3/082 ,  G06N3/084 ,  H01L23/31 ,  H01L25/04 ,  H01L25/065 ,  H01L23/00 ,  H01L25/07 ,  H01L25/075 ,  H01L25/11 ,  H03K19/21

    Abstract: Some embodiments provide a three-dimensional (3D) circuit structure that has two or more vertically stacked bonded layers with a machine-trained network on at least one bonded layer. As described above, each bonded layer can be an IC die or an IC wafer in some embodiments with different embodiments encompassing different combinations of wafers and dies for the different bonded layers. The machine-trained network in some embodiments includes several stages of machine-trained processing nodes with routing fabric that supplies the outputs of earlier stage nodes to drive the inputs of later stage nodes. In some embodiments, the machine-trained network is a neural network and the processing nodes are neurons of the neural network. In some embodiments, one or more parameters associated with each processing node (e.g., each neuron) is defined through machine-trained processes that define the values of these parameters in order to allow the machine-trained network (e.g., neural network) to perform particular operations (e.g., face recognition, voice recognition, etc.). For example, in some embodiments, the machine-trained parameters are weight values that are used to aggregate (e.g., to sum) several output values of several earlier stage processing nodes to produce an input value for a later stage processing node.

    3D NAND - HIGH ASPECT RATIO STRINGS AND CHANNELS
    9.
    发明申请
    3D NAND - HIGH ASPECT RATIO STRINGS AND CHANNELS 有权

    公开(公告)号：US20250048633A1

    公开(公告)日：2025-02-06

    申请号：US18738438

    申请日：2024-06-10

    Applicant: Adeia Semiconductor Inc.

    Inventor： Rajesh Katkar ,  Xu Chang ,  Belgacem Haba

    IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

    Abstract: Aspects of the disclosure relate to forming a completed stack of layers. Forming the completed stack of layers may include forming a first stack of layers on a first substrate and forming a second stack of layers on a second substrate. The first stack of layers may be bonded to the second stack of layers. The first or second substrate may be removed. Prior to bonding the first stack of layers and the second stack of layer, one or more holes may be etched in the first stack of layers. After removing the second substrate, one or more holes may be etched in the second stack of layers, wherein each of the one or more holes in the second stack of layers extend into a corresponding hole in the one or more holes in the first stack of layers.

    3D NAND—high aspect ratio strings and channels
    10.
    发明授权
    3D NAND—high aspect ratio strings and channels 有权

    公开(公告)号：US12035529B2

    公开(公告)日：2024-07-09

    申请号：US17851943

    申请日：2022-06-28

    Applicant: Adeia Semiconductor Inc.

    Inventor： Rajesh Katkar ,  Xu Chang ,  Belgacem Haba

    IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

    CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

    Abstract: Aspects of the disclosure relate to forming a completed stack of layers. Forming the completed stack of layers may include forming a first stack of layers on a first substrate and forming a second stack of layers on a second substrate. The first stack of layers may be bonded to the second stack of layers. The first or second substrate may be removed. Prior to bonding the first stack of layers and the second stack of layer, one or more holes may be etched in the first stack of layers. After removing the second substrate, one or more holes may be etched in the second stack of layers, wherein each of the one or more holes in the second stack of layers extend into a corresponding hole in the one or more holes in the first stack of layers.

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