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公开(公告)号：US20240330205A1
公开(公告)日：2024-10-03
申请号：US18129305
申请日：2023-03-31
Applicant: ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
CPC classification number: G06F12/1408 , G06F21/72 , H04L9/14 , G06F2212/1052
Abstract: A processing system includes one or more storage encryption circuits (SIECs) interconnected with one or more input/output (I/O) devices and a system memory. Each SIEC is configured to encrypt and decrypt data as the data passes between the I/O devices and the system memory. To this end, an SIEC includes slots each associated with respective memory addresses of the system memory. Each slot provides an aperture to the associated memory addresses such that the I/O devices use these apertures to indirectly target the associated memory addresses. As the data targeting the memory addresses associated with an aperture passes through an SIEC, the SIEC encrypts or decrypts the data using cryptographic keys stored on the SIEC.
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公开(公告)号：US12105666B2
公开(公告)日：2024-10-01
申请号：US17234191
申请日：2021-04-19
Applicant: Advanced Micro Devices, Inc. , ATI TECHNOLOGIES ULC
Inventor： Shijie Che , Wentao Xu , Randall Brown , Vaibhav Amarayya Hiremath , Manuchehr Taghi-Loo
IPC: G06F9/38 , G06F15/177 , H04L41/0893
CPC classification number: G06F15/177 , G06F9/3877 , H04L41/0893
Abstract: A computing system may implement a method for creating a first subdomain by configuring one of a first plurality of slave nodes as a first subdomain master node and configuring one or more other slave nodes of the first plurality of slave nodes as first subdomain slave nodes to the first subdomain master node.
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公开(公告)号：US20240323451A1
公开(公告)日：2024-09-26
申请号：US18189831
申请日：2023-03-24
Applicant: ATI Technologies ULC
Inventor： Ihab M. A. Amer , Konstantin Moskvitin , Haibo Liu , Mehdi Saeedi , Ho Hin Lau , Mehdi Semsarzadeh
IPC: H04N19/85 , H04N19/12 , H04N19/13 , H04N19/156 , H04N19/176 , H04N19/61
CPC classification number: H04N19/85 , H04N19/12 , H04N19/13 , H04N19/156 , H04N19/176 , H04N19/61
Abstract: A technique for performing video operations is provided. The technique includes decoding underlying content to obtain a decoded block; and applying a shade pattern to the decoded block to obtain a final block.
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公开(公告)号：US20240319760A1
公开(公告)日：2024-09-26
申请号：US18126166
申请日：2023-03-24
Applicant: ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
Inventor： Ian Charles Colbert , Alexander Sabino Duenas , Stephen Jiacheng Fu , Omer Irshad , Mohammad Hamed Mousazadeh , Ihab Amer , Gabor Sines
Abstract: A processing device includes an automated overclocking system and a processor. The automated overclocking system is data-driven and includes an inference engine that executes a machine learning model configured to generate a first output based on a current configuration of the processing device. The first output includes a first set of overclocking parameters. The processor is configured to adjust one or more operating characteristics of at least one component of the processing device based on the first set of overclocking parameters.
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公开(公告)号：US12073806B2
公开(公告)日：2024-08-27
申请号：US17134770
申请日：2020-12-28
Applicant: ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
Inventor： Ashish Jain , Dhirendra Partap Singh Rana , Samuel Naffziger , Gia Tung Phan , Benjamin Tsien
IPC: G09G3/36 , G06F1/3234 , G06F12/0811 , G06F12/0895 , G09G3/20
CPC classification number: G09G3/3618 , G06F1/3265 , G06F12/0811 , G06F12/0895 , G09G3/2092 , G09G2330/021
Abstract: Refreshing displays using on-die cache, including: determining that a static display condition has been met; storing, in cache memory of a processor, first display data; and displaying the first display data from the cache memory.
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Patent Agency Ranking
公开(公告)号：US20240273767A1
公开(公告)日：2024-08-15
申请号：US18434185
申请日：2024-02-06
Applicant: ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
Inventor： Saurabh SHARMA , Laurent LEFEBVRE , Sagar Shankar BHANDARE , Ruijin WU
CPC classification number: G06T9/00 , G06T1/60 , G06T2200/04
Abstract: Sampling circuitry independently accesses channels of texture data that represent a set of pixels. One or more processing units separately compress the channels of the texture data and store compressed data representative of the channels of the texture data for the set of pixels. The channels can include a red channel, a blue channel, and a green channel that represent color values of the set of pixels and an alpha channel that represents degrees of transparency of the set of pixels. Storing the compressed data can include writing the compress data to portions of a cache. The processing units can identify a subset of the set of pixels that share a value of a first channel of the plurality of channels and represent the value of the first channel over the subset of the set of pixels using information representing the value, the first channel, and boundaries of the subset.
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公开(公告)号：US20240250051A1
公开(公告)日：2024-07-25
申请号：US18627896
申请日：2024-04-05
Applicant: ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
Inventor： SUMING HU , FARSHAD GHAHGHAHI
IPC: H01L23/00
CPC classification number: H01L24/13 , H01L24/11 , H01L24/16 , H01L2224/11622 , H01L2224/13006 , H01L2224/13018 , H01L2224/13541 , H01L2224/13552 , H01L2224/13582 , H01L2224/16227 , H01L2224/16238
Abstract: In an implementation, a semiconductor chip includes a device layer, an interconnect layer fabricated on the device layer, the interconnect layer including a conductive pad, and a conductive pillar coupled to the conductive pad. The conductive pillar includes at least a first portion having a first width and a second portion having a second width, the first portion being disposed between the second portion and the conductive pad, wherein the first width of the first portion is greater than the second width of the second portion.
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公开(公告)号：US12045675B2
公开(公告)日：2024-07-23
申请号：US16457237
申请日：2019-06-28
Applicant: ATI Technologies ULC
Inventor： Tung Chuen Kwong , Clarence Ip , Benjamin Koon Pan Chan , Edward Lee Kim-Koon , Meghana Manjunatha
CPC classification number: G06F9/545 , G06F9/30036 , G06F9/3877 , G06F9/5072 , G06F9/541 , G06F11/3672
Abstract: Systems, apparatuses, and methods for implementing a safety monitor framework for a safety-critical graphics processing unit (GPU) compute application are disclosed. A system includes a safety-critical GPU compute application, a safety monitor, and a GPU. The safety monitor receives a compute grid, test vectors, and a compute kernel from the safety-critical GPU compute application. The safety monitor generates a modified compute grid by adding extra tiles to the original compute grid, with the extra tiles generated based on the test vectors. The safety monitor provides the modified compute grid and compute kernel to the GPU for processing. The safety monitor determines the likelihood of erroneous processing of the original compute grid by comparing the actual results for the extra tiles with known good results. The safety monitor complements the overall fault coverage of the GPU hardware and covers faults only observable at the application programming interface (API) level.
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公开(公告)号：US12033273B2
公开(公告)日：2024-07-09
申请号：US17972307
申请日：2022-10-24
Applicant: ATI TECHNOLOGIES ULC
Inventor： David I. J. Glen , Keith Lee
CPC classification number: G06T15/503 , G06T7/90 , G06T11/001 , G06T2210/62
Abstract: In some examples, an apparatus obtains source layer pixels, such as those of a content image and first destination layer pixels, such as those of a destination image. The first destination layer pixels have associated alpha values. The apparatus obtains information that indicates a first blending color format for the alpha values. The first blending color format is different from a first destination layer color format for the first destination layer pixels and an output color format for a display. The apparatus converts the source and/or first destination layer pixels to the first blending color format. The apparatus generates first alpha blended pixels based on alpha blending the source layer pixels with the first destination layer pixels using the associated alpha values. The apparatus provides, for display on the display, the first alpha blended pixels.
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公开(公告)号：US20240214246A1
公开(公告)日：2024-06-27
申请号：US18086960
申请日：2022-12-22
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Pradeep Jayaraman , Karthik Gopalakrishnan , Andrew Egli
CPC classification number: H04L25/03038 , H04L25/4917 , H04L2025/03471
Abstract: A driver circuit includes a feed-forward equalization (FFE) circuit. The FFE circuit receives a plurality of pulse-amplitude modulation (PAM) symbol values to be transmitted at one of multiple PAM levels. The FFE circuit includes a first partial lookup table, one or more additional partial lookup tables, and an adder circuit. The first partial lookup table contains partial finite impulse-response (FIR) values and indexed based on a current PAM symbol value, a precursor PAM symbol value, and a postcursor PAM symbol value. The one or more additional partial lookup tables each contain partial FIR values and indexed based on a respective additional one or more of the PAM symbol values. The adder circuit adds results of lookups from the first partial lookup table and the additional partial lookup tables to produce an output value.
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