公开(公告)号：US06939734B2

公开(公告)日：2005-09-06

申请号：US10820652

申请日：2004-04-08

Applicant: Martin Franosch ,  Andreas Meckes ,  Klaus-Günter Oppermann

Inventor： Martin Franosch ,  Andreas Meckes ,  Klaus-Günter Oppermann

IPC: B81B7/00 ,  H03H3/007 ,  H03H9/02 ,  H01L21/00

CPC classification number: B81C1/00333 ,  B81C2203/0136 ,  H01L2224/11 ,  H03H3/007 ,  H03H9/02834 ,  H03H9/02984

Abstract: In a method for producing a protective cover for a device which is formed in a substrate, a first cover layer is initially deposited on the substrate, the first cover layer covering an area of the substrate which includes the device. Subsequently, an opening is formed in the first cover layer, the opening exposing that area of the substrate which includes the device. Then the opening formed in the first cover layer is filled up using a filling material. Subsequently, a second cover layer is deposited on the first cover layer and in the opening of the first cover layer which is filled up with the filling material. Thereafter, an opening is formed in the second cover layer to expose an area of the filling material. Finally, the filling material covering that area of the substrate which includes the device is removed, and the opening formed in the second cover layer is closed.

Abstract translation: 在用于制造形成在基板中的装置的保护罩的方法中，首先在基板上沉积第一覆盖层，第一覆盖层覆盖包括该装置的基板的区域。 随后，在第一覆盖层中形成开口，该开口露出包括该装置的基板的该区域。 然后，使用填充材料填充形成在第一覆盖层中的开口。 随后，在填充有填充材料的第一覆盖层和第一覆盖层的开口中沉积第二覆盖层。 此后，在第二覆盖层中形成开口以露出填充材料的区域。 最后，除去覆盖包括该装置的基板的区域的填充材料，并且形成在第二覆盖层中的开口被封闭。

公开(公告)号：US06867105B2

公开(公告)日：2005-03-15

申请号：US10215152

申请日：2002-08-08

Applicant: Reinhard Stengl ,  Thomas Meister ,  Herbert Schäfer ,  Martin Franosch

Inventor： Reinhard Stengl ,  Thomas Meister ,  Herbert Schäfer ,  Martin Franosch

IPC: H01L21/331 ,  H01L29/732

CPC classification number: H01L29/66287 ,  H01L29/7322

Abstract: A bipolar transistor includes a first layer with a collector. A second layer has a base cutout for a base. A third layer includes a lead for the base. The third layer is formed with an emitter cutout for an emitter. An undercut is formed in the second layer adjoining the base cutout. The base is at least partially located in the undercut. In order to obtain a low transition resistance between the lead and the base, an intermediate layer is provided between the first and the second layer. The intermediate layer is selectively etchable with respect to the second layer. At least in the region of the undercut between the lead and the base, a base connection zone is provided that can be adjusted independent of other production conditions. The intermediate layer is removed in a contact region with the base.

Abstract translation: 双极晶体管包括具有集电极的第一层。 第二层具有用于基座的基部切口。 第三层包括用于底座的引线。 第三层形成有用于发射极的发射极切口。 在与基座切口相邻的第二层中形成底切。 基部至少部分位于底切中。 为了在引线和基底之间获得低的过渡电阻，在第一和第二层之间设置中间层。 中间层相对于第二层可选择性地蚀刻。 至少在引线和基座之间的底切区域中，提供可以独立于其他生产条件进行调节的基础连接区域。 在与基底的接触区域中去除中间层。

公开(公告)号：US6117790A

公开(公告)日：2000-09-12

申请号：US302655

申请日：1999-04-30

Applicant: Herbert Schafer ,  Martin Franosch ,  Reinhard Stengl ,  Gerrit Lange ,  Hans Reisinger ,  Hermann Wendt ,  Volker Lehmann

Inventor： Herbert Schafer ,  Martin Franosch ,  Reinhard Stengl ,  Gerrit Lange ,  Hans Reisinger ,  Hermann Wendt ,  Volker Lehmann

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/00

CPC classification number: H01L27/10852 ,  H01L27/10817 ,  H01L28/82

Abstract: A method for fabricating a capacitor for a semiconductor memory configuration. In this case, a selectively etchable material is applied to a conductive support, which is connected to a semiconductor body via a contact hole in an insulator layer, and patterned. A first conductive layer is applied thereon and patterned. A hole is introduced into the first conductive layer, through which hole the selectively etchable material is etched out. A cavity is produced under the first conductive layer in the process. The inner surface of the cavity and the outer surface of the first conductive layer are provided with a dielectric layer, to which a second conductive layer is applied and patterned.

Abstract translation: 一种制造用于半导体存储器配置的电容器的方法。 在这种情况下，将可选择的可蚀刻材料施加到导电支撑件，该导电支撑件通过绝缘体层中的接触孔连接到半导体本体并且被图案化。 在其上施加第一导电层并图案化。 在第一导电层中引入一个孔，通过该孔蚀刻可选择性蚀刻的材料。 在该过程中在第一导电层下方产生空腔。 空腔的内表面和第一导电层的外表面设置有电介质层，第二导电层被施加并图案化。

公开(公告)号：US08618621B2

公开(公告)日：2013-12-31

申请号：US12938568

申请日：2010-11-03

Applicant: Klaus-Guenter Oppermann ,  Martin Franosch ,  Martin Handtmann

Inventor： Klaus-Guenter Oppermann ,  Martin Franosch ,  Martin Handtmann

IPC: H01L29/84

CPC classification number: H03H9/02125 ,  H01L21/6835 ,  H01L23/3121 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68368 ,  H01L2224/0401 ,  H01L2224/11002 ,  H01L2224/16225 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01072 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/1421 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An apparatus comprises a device layer structure, a device integrated into the device layer structure, an insulating carrier substrate and an insulating layer being continuously positioned between the device layer structure and the insulating carrier substrate, the insulating layer having a thickness which is less than 1/10 of a thickness of the insulating carrier substrate. An apparatus further comprises a device integrated into a device layer structure disposed on an insulating layer, a housing layer disposed on the device layer structure and housing the device, a contact providing an electrical connection between the device and a surface of the housing layer opposed to the device layer structure and a molding material surrounding the housing layer and the insulating layer, the molding material directly abutting on a surface of the insulating layer being opposed to the device layer structure.

Abstract translation: 一种装置包括器件层结构，集成到器件层结构中的器件，绝缘载体衬底和绝缘层，其连续地位于器件层结构和绝缘载体衬底之间，绝缘层的厚度小于1 绝缘载体基板的厚度的1/10。 一种装置还包括集成在设置在绝缘层上的器件层结构中的器件，设置在器件层结构上并容纳该器件的壳体层，提供该器件与壳体层相对的表面之间的电连接的触点 所述器件层结构和围绕所述壳体层和所述绝缘层的模制材料，所述模制材料直接邻接在所述绝缘层的与所述器件层结构相对的表面上。

公开(公告)号：US20120074405A1

公开(公告)日：2012-03-29

申请号：US13314595

申请日：2011-12-08

Applicant: Herbert Schäfer ,  Martin Franosch ,  Thomas Meister ,  Josef Böck

Inventor： Herbert Schäfer ,  Martin Franosch ,  Thomas Meister ,  Josef Böck

IPC: H01L29/06 ,  H01L21/20

CPC classification number: H01L21/02639 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/02661

Abstract: One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.

Abstract translation: 本发明的一个实施例涉及利用原位差分外延在半导体主体上同时沉积多个不同结晶结构的方法。 在本发明的一个实施方案中，形成制备表面，得到两个不同的结晶区域，单晶硅衬底区域和隔离层区域。 单晶硅层和非晶硅层同时直接分布在单晶硅衬底区域和隔离层区域的制备表面上。 沉积包括形成两个或更多个子层。 可以为每个单独的子层改变工艺参数以优化沉积特性。

公开(公告)号：US07612430B2

公开(公告)日：2009-11-03

申请号：US10297421

申请日：2001-06-15

Applicant: Martin Franosch ,  Thomas Meister ,  Herbert Schäfer ,  Reinhard Stengl ,  Konrad Wolf

Inventor： Martin Franosch ,  Thomas Meister ,  Herbert Schäfer ,  Reinhard Stengl ,  Konrad Wolf

IPC: H01L29/732

CPC classification number: H01L29/1004

Abstract: The silicon bipolar transistor (100) comprises a base, with a first highly-doped base layer (105) and a second poorly-doped base layer (106) which together form the base. The emitter is completely highly-doped and mounted directly on the second base layer (106).

Abstract translation: 硅双极晶体管（100）包括具有一起形成基极的第一高掺杂基极层（105）和第二较差掺杂的基极层（106）的基极。 发射极是完全高度掺杂的，直接安装在第二基极层（106）上。

公开(公告)号：US20090179333A1

公开(公告)日：2009-07-16

申请号：US11972793

申请日：2008-01-11

Applicant: Alfred Martin ,  Barbara Hasler ,  Martin Franosch ,  Klaus-Guenter Oppermann

Inventor： Alfred Martin ,  Barbara Hasler ,  Martin Franosch ,  Klaus-Guenter Oppermann

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H05K3/3452 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05616 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06136 ,  H01L2224/10125 ,  H01L2224/10145 ,  H01L2224/11013 ,  H01L2224/11332 ,  H01L2224/11334 ,  H01L2224/11422 ,  H01L2224/11622 ,  H01L2224/1181 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/8109 ,  H01L2224/81205 ,  H01L2224/8123 ,  H01L2224/81815 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01067 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K3/3484 ,  H05K2201/0989 ,  H05K2201/2081 ,  H05K2203/043 ,  H01L2924/00014 ,  H01L2224/05552

Abstract: An integrated circuit that comprises a substrate and a structured layer on the substrate. The structured layer comprises an opening to the substrate, a first field and a second field on the substrate, wherein the first field and the second field, at least in part, overlap with the opening. The integrated circuit further comprises a first material in the area of the first field and a second material in the area of the second field. The first material impedes a wetting by a solder material, and the second provides a wetting by the solder material.

Abstract translation: 一种集成电路，包括衬底和衬底上的结构化层。 所述结构化层包括到所述衬底的开口，所述衬底上的第一场和第二场，其中所述第一场和所述第二场至少部分地与所述开口重叠。 集成电路还包括第一场区域中的第一材料和第二场区域中的第二材料。 第一种材料阻碍焊料材料的润湿，第二种材料通过焊料材料而被润湿。

公开(公告)号：US20090026607A1

公开(公告)日：2009-01-29

申请号：US11781282

申请日：2007-07-23

Applicant: Holger HUEBNER ,  Martin FRANOSCH

Inventor： Holger HUEBNER ,  Martin FRANOSCH

IPC: H01L23/48 ,  H01L21/00

CPC classification number: H05K3/305 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/12 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83194 ,  H01L2224/8383 ,  H01L2224/83862 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/15788 ,  H05K3/284 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2203/0783 ,  H05K2203/306 ,  Y02P70/613 ,  H01L2924/00

Abstract: It is proposed a method of manufacturing an electronic system wherein a first substrate comprising first connection elements on a first surface of the first substrate is provided; a second substrate comprising second connection elements on a first surface of the second substrate is provided; a polymer layer is applied to at least one of the two first surfaces; the first connection elements are attached to the second connection elements; and the polymer layer is caused to swell during or after the attachment.

Abstract translation: 提出了一种制造电子系统的方法，其中提供包括在第一基板的第一表面上的第一连接元件的第一基板; 提供包括在第二基板的第一表面上的第二连接元件的第二基板; 将聚合物层施加到两个第一表面中的至少一个上; 第一连接元件附接到第二连接元件; 并且在附着期间或之后使聚合物层膨胀。

公开(公告)号：US20070182029A1

公开(公告)日：2007-08-09

申请号：US11672760

申请日：2007-02-08

Applicant: Martin Franosch ,  Andreas Meckes ,  Edward Fuergut

Inventor： Martin Franosch ,  Andreas Meckes ,  Edward Fuergut

IPC: H01L23/29

CPC classification number: B81C1/00269 ,  B81C1/00333 ,  B81C2203/0136 ,  H01L21/50 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/552 ,  H01L24/28 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/16235 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/3025 ,  H03H9/0523 ,  H03H9/1007 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor is disclosed. In one embodiment, the semiconductor includes a semiconductor substrate having an active area region, a covering configured to protect the active area region, and a carrier. An interspace is located between the carrier and the covering. The interspace is filled with an underfiller material is disclosed.

Abstract translation: 公开了半导体。 在一个实施例中，半导体包括具有有源区域区域的半导体衬底，被配置为保护有源区域区域的覆盖物和载体。 一个间隙位于载体和覆盖物之间。 公开了填充有底填料的间隙。

公开(公告)号：US20060183325A1

公开(公告)日：2006-08-17

申请号：US11331434

申请日：2006-01-12

Applicant: Martin Franosch ,  Klaus-Guenter Oppermann

Inventor： Martin Franosch ,  Klaus-Guenter Oppermann

IPC: H01L21/44

CPC classification number: H01L21/0272 ,  G03F7/38 ,  G03F7/40

Abstract: A lift-off method includes providing a material structure, applying photoresist on a surface of the material structure, partially exposing the photoresist, baking the material structure with the partially exposed photoresist applied on the surface of the material structure, developing the photoresist with an organic, polar developer, so that the photoresist is removed in a first region of the surface, and the photoresist remains in the second region of the surface, applying coating material on the surface of the material structure and the remaining photoresist, and removing the photoresist.

Abstract translation: 剥离方法包括提供材料结构，在材料结构的表面上施加光致抗蚀剂，部分地曝光光致抗蚀剂，用施加在材料结构表面上的部分曝光的光致抗蚀剂烘烤材料结构，用有机 极性显影剂，使得在表面的第一区域中去除光致抗蚀剂，并且光致抗蚀剂保留在表面的第二区域中，将涂料涂覆在材料结构的表面上，并除去光致抗蚀剂。