公开(公告)号：US20080022068A1

公开(公告)日：2008-01-24

申请号：US11489079

申请日：2006-07-18

Applicant: Martin Taillefer

Inventor： Martin Taillefer

IPC: G06F12/00

CPC classification number: G06F12/1009 ,  G06F12/109

Abstract: Guest logical to physical translation is leveraged for host-side memory access. A contiguous portion of host physical address space is dedicated to the guest operating system. A reusable offset value may be calculated upon guest operating system initialization. Everything stored in the guest “physical” address space can be directly mapped to the contiguous portion of host physical address space using the reusable offset value, if necessary, thereby greatly reducing mapping complexity for both store and look-up operations.

公开(公告)号：US09092253B2

公开(公告)日：2015-07-28

申请号：US12638345

申请日：2009-12-15

Applicant: Martin Taillefer ,  Jan Gray ,  Richard Wurdack ,  Gad Sheaffer ,  Ali-Reza Adl Tabatabai

Inventor： Martin Taillefer ,  Jan Gray ,  Richard Wurdack ,  Gad Sheaffer ,  Ali-Reza Adl Tabatabai

IPC: G06F9/44 ,  G06F9/46 ,  G06F11/36 ,  G06F11/34

CPC classification number: G06F9/467 ,  G06F11/3409 ,  G06F11/3466 ,  G06F11/3612 ,  G06F11/3636 ,  G06F11/3648 ,  G06F2201/86 ,  G06F2201/87 ,  G06F2201/88 ,  G06F2201/885

Abstract: Monitoring performance of one or more architecturally significant processor caches coupled to a processor. The methods include executing an application on one or more processors coupled to one or more architecturally significant processor caches, where the application utilizes the architecturally significant portions of the architecturally significant processor caches. The methods further include at least one of generating metrics related to performance of the architecturally significant processor caches; implementing one or more debug exceptions related to performance of the architecturally significant processor caches; or implementing one or more transactional breakpoints related to performance of the architecturally significant processor caches as a result of utilizing the architecturally significant portions of the architecturally significant processor caches.

Abstract translation: 监视耦合到处理器的一个或多个架构上重要的处理器高速缓存的性能。 所述方法包括在耦合到一个或多个架构有意义的处理器高速缓存的一个或多个处理器上执行应用，其中应用利用架构上重要的处理器高速缓存的架构上重要的部分。 所述方法还包括生成与架构上重要的处理器高速缓存的性能有关的度量中的至少一个; 实现与架构上重要的处理器高速缓存的性能相关的一个或多个调试异常; 或者通过利用架构上重要的处理器高速缓存的架构上重要的部分来实现与架构上重要的处理器高速缓存的性能相关的一个或多个事务性断点。

公开(公告)号：US08688951B2

公开(公告)日：2014-04-01

申请号：US13554558

申请日：2012-07-20

Applicant: Koichi Yamada ,  Gad Sheaffer ,  Ali-Reza Adl-Tabatabai ,  Landy Wang ,  Martin Taillefer ,  Arun Kishan ,  David Callahan ,  Jan Gray ,  Vadim Bassin

Inventor： Koichi Yamada ,  Gad Sheaffer ,  Ali-Reza Adl-Tabatabai ,  Landy Wang ,  Martin Taillefer ,  Arun Kishan ,  David Callahan ,  Jan Gray ,  Vadim Bassin

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F9/26 ,  G06F9/34 ,  G06F9/455 ,  G06F9/46

CPC classification number: G06F12/1045 ,  G06F12/0815

Abstract: Operating system virtual memory management for hardware transactional memory. A system includes an operating system deciding to unmap a first virtual page. As a result, the operating system removes the mapping of the first virtual page to the first physical page from the virtual memory page table. As a result, the operating system performs an action to discard transactional memory hardware state for at least the first physical page. Embodiments may further suspend hardware transactions in kernel mode. Embodiments may further perform soft page fault handling without aborting a hardware transaction, resuming the hardware transaction upon return to user mode, and even successfully committing the hardware transaction.

Abstract translation: 硬件事务内存的操作系统虚拟内存管理。 系统包括决定取消映射第一虚拟页面的操作系统。 结果，操作系统从虚拟存储器页表移除第一虚拟页面到第一物理页面的映射。 结果，操作系统执行至少第一物理页丢弃事务存储器硬件状态的动作。 实施例可以进一步挂起内核模式下的硬件事务。 实施例可以进一步执行软页错误处理，而不中止硬件事务，在返回到用户模式时恢复硬件事务，甚至成功地提交硬件事务。

公开(公告)号：US08521995B2

公开(公告)日：2013-08-27

申请号：US12638064

申请日：2009-12-15

Applicant: Koichi Yamada ,  Gad Sheaffer ,  Jan Gray ,  Landy Wang ,  Martin Taillefer ,  Arun Kishan ,  Ali-Reza Adl-Tabatabai ,  David Callahan

Inventor： Koichi Yamada ,  Gad Sheaffer ,  Jan Gray ,  Landy Wang ,  Martin Taillefer ,  Arun Kishan ,  Ali-Reza Adl-Tabatabai ,  David Callahan

IPC: G06F13/14

CPC classification number: G06F9/3834 ,  G06F9/30076 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/461 ,  G06F9/467 ,  G06F9/4812 ,  G06F2209/481

Abstract: A method includes receiving control in a kernel mode via a ring transition from a user thread during execution of an unbounded transactional memory (UTM) transaction, updating a state of a transaction status register (TSR) associated with the user thread and storing the TSR with a context of the user thread, and later restoring the context during a transition from the kernel mode to the user thread. In this way, the UTM transaction may continue on resumption of the user thread.

Abstract translation: 一种方法包括：在执行无界事务存储器（UTM）事务期间，通过来自用户线程的环转移接收控制，更新与用户线程相关联的事务状态寄存器（TSR）的状态并将TSR与 用户线程的上下文，然后在从内核模式到用户线程的转换期间恢复上下文。 以这种方式，UTM事务可以继续恢复用户线程。

公开(公告)号：US08402218B2

公开(公告)日：2013-03-19

申请号：US12638929

申请日：2009-12-15

Applicant: Jan Gray ,  Martin Taillefer ,  Yosseff Levanoni ,  Ali-Reza Adl-Tabatabai ,  Dave Detlefs ,  Vinod K. Grover ,  Michael Magruder ,  Gad Sheaffer

Inventor： Jan Gray ,  Martin Taillefer ,  Yosseff Levanoni ,  Ali-Reza Adl-Tabatabai ,  Dave Detlefs ,  Vinod K. Grover ,  Michael Magruder ,  Gad Sheaffer

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F9/466 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/30185 ,  G06F9/3834 ,  G06F9/467 ,  G06F12/0253 ,  G06F12/0815 ,  G06F12/082

Abstract: Handling garbage collection and exceptions in hardware assisted transactions. Embodiments are practiced in a computing environment including a hardware assisted transaction system. Embodiments includes acts for writing to a card table outside of a transaction; handling garbage collection compaction occurring when a hardware transaction is active by using a common global variable and instructing one or more agents to write to the common global variable any time an operation is performed which may change an object's virtual address; acts for managing a thread-local allocation context; acts for handling exceptions while in a hardware assisted transaction. A method includes beginning a hardware assisted transaction, raising an exception while in the hardware assisted transaction, including creating an exception object, determining that the transaction should be rolled back, and as a result of determining that the transaction should be rolled back, marshaling the exception object out of the hardware assisted transaction.

Abstract translation: 在硬件辅助交易中处理垃圾收集和异常。 实施例在包括硬件辅助交易系统的计算环境中实现。 实施例包括用于在事务之外写入卡表的动作; 通过使用公共全局变量来处理在硬件事务处于活动状态时发生的垃圾收集压缩，并且在每次执行可能改变对象的虚拟地址的操作时，指示一个或多个代理写入公共全局变量; 用于管理线程本地分配上下文的动作; 在硬件辅助交易中处理异常的行为。 一种方法包括开始硬件辅助事务，在硬件辅助事务中引发异常，包括创建异常对象，确定事务应该回滚，并且由于确定事务应该回滚，因此， 异常对象出来的硬件辅助事务。

公开(公告)号：US08356166B2

公开(公告)日：2013-01-15

申请号：US12493168

申请日：2009-06-26

Applicant: Ali-Reza Adl-Tabatabai ,  Bratin Saha ,  Gad Sheaffer ,  Vadim Bassin ,  Robert Y. Geva ,  Martin Taillefer ,  Darek Mihocka ,  Burton Jordan Smith ,  Jan Gray

Inventor： Ali-Reza Adl-Tabatabai ,  Bratin Saha ,  Gad Sheaffer ,  Vadim Bassin ,  Robert Y. Geva ,  Martin Taillefer ,  Darek Mihocka ,  Burton Jordan Smith ,  Jan Gray

IPC: G06F15/00 ,  G06F9/00 ,  G06F9/44 ,  G06F7/38

CPC classification number: G06F9/3004 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/30101 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3857 ,  G06F9/467

Abstract: Minimizing code duplication in an unbounded transactional memory system. A computing apparatus including one or more processors in which it is possible to use a set of common mode-agnostic TM barrier sequences that runs on legacy ISA and extended ISA processors, and that employs hardware filter indicators (when available) to filter redundant applications of TM barriers, and that enables a compiled binary representation of the subject code to run correctly in any of the currently implemented set of transactional memory execution modes, including running the code outside of a transaction, and that enables the same compiled binary to continue to work with future TM implementations which may introduce as yet unknown future TM execution modes.

Abstract translation: 最大限度地减少无界事务内存系统中的代码重复。 一种包括一个或多个处理器的计算设备，其中可以使用在传统ISA和扩展ISA处理器上运行的一组共同模式不可知TM屏障序列，并且采用硬件滤波器指示器（当可用时）可以过滤冗余应用 TM屏障，并且使得主体代码的编译二进制表示可以在任何当前实现的事务存储器执行模式集中运行，包括在事务之外运行代码，并且使得相同的编译的二进制文件能够继续工作 与未来的TM实现可能会引入未知的未来TM执行模式。

公开(公告)号：US08266387B2

公开(公告)日：2012-09-11

申请号：US11823212

申请日：2007-06-27

Applicant: Martin Taillefer ,  Darek Mihocka ,  Bruno Silva

Inventor： Martin Taillefer ,  Darek Mihocka ,  Bruno Silva

IPC: G06F12/00 ,  G06F9/445

CPC classification number: G06F9/45533

Abstract: Various technologies and techniques are disclosed for using transactional memory hardware to accelerate virtualization or emulation. One or more central processing units are provided with transactional memory hardware that is operable to accelerate virtualization. The transactional memory hardware has a facility to maintain private state, a facility to render memory accesses from other central processing units visible to software, and support for atomic commit of the private state. The transactional memory hardware can be used, for example, to facilitate emulation of precise exception semantics. The private state is operable to enable an emulated state to remain inconsistent with an architectural state and only synchronized on certain boundaries. An optimized sequence of instructions is executed using chunk-accurate simulation to try and achieve a same end effect.

Abstract translation: 公开了用于使用事务性存储器硬件来加速虚拟化或仿真的各种技术和技术。 一个或多个中央处理单元设置有可操作以加速虚拟化的事务存储器硬件。 事务性存储器硬件具有维护私有状态的功能，用于使得对软件可见的其它中央处理单元进行存储器访问的设施，以及对私有状态的原子提交的支持。 例如，可以使用事务性存储器硬件来促进精确异常语义的仿真。 私有状态可操作以使仿真状态与架构状态保持不一致，并且仅在某些边界上同步。 使用块精确模拟来执行优化的指令序列，以尝试并实现相同的最终效果。

公开(公告)号：US08099719B2

公开(公告)日：2012-01-17

申请号：US11820284

申请日：2007-06-19

Applicant: Martin Taillefer

Inventor： Martin Taillefer

IPC: G06F9/44 ,  G06F9/45

CPC classification number: G06F11/3664

Abstract: Various technologies and techniques are disclosed for providing a debugger for programs running under a transactional memory system. When running a particular program using the debugger, the system detects when a conflict occurs on at least one conflictpoint that was set in the particular program. A graphical user interface is provided that displays information related to the detected conflict. The graphical user interface can display transactional state and/or other details independently of a conflict. A conflictpoint can be assigned to one or more regions of source code in one or more transactions in the particular program. A conflictpoint can also be assigned to a particular variable in the particular program. When running the particular program in a debug mode, execution is stopped if a conflict occurs on any of the conflictpoints.

Abstract translation: 公开了各种技术和技术，以提供用于在事务存储器系统下运行的程序的调试器。 当使用调试器运行特定程序时，系统将检测在特定程序中设置的至少一个冲突点上何时发生冲突。 提供了一种图形用户界面，显示与检测到的冲突有关的信息。 图形用户界面可以独立于冲突来显示事务状态和/或其他细节。 可以在特定程序中的一个或多个事务中将冲突点分配给源代码的一个或多个区域。 冲突点也可以分配给特定程序中的特定变量。 当以调试模式运行特定程序时，如果任何冲突点发生冲突，则停止执行。

公开(公告)号：US20110161603A1

公开(公告)日：2011-06-30

申请号：US13043082

申请日：2011-03-08

Applicant: Martin Taillefer

Inventor： Martin Taillefer

IPC: G06F12/14

CPC classification number: G06F9/466

Abstract: Various technologies and techniques are described for providing a transaction grouping feature for use in programs operating under a transactional memory system. The transaction grouping feature is operable to allow transaction groups to be created that contain related transactions. The transaction groups are used to enhance performance and/or operation of the programs. Different locking and versioning mechanisms can be used with different transaction groups. When running transactions, a hardware transactional memory execution mechanism can be used for one transaction group while a software transactional memory execution mechanism used for another transaction group.

Abstract translation: 描述了用于提供用于在事务存储器系统下操作的程序中的事务分组特征的各种技术和技术。 事务分组功能可操作以允许创建包含相关事务的事务组。 交易组用于增强程序的性能和/或操作。 不同的锁定和版本控制机制可以与不同的事务组一起使用。 运行事务时，硬件事务内存执行机制可用于一个事务组，而另一个事务组则使用软件事务内存执行机制。

公开(公告)号：US20110145798A1

公开(公告)日：2011-06-16

申请号：US12646438

申请日：2009-12-23

Applicant: Martin Taillefer ,  Ali-Reza Adl-Tabatabai ,  Gad Sheaffer ,  Peter Lachner ,  Richard Wurdack ,  Darek Mihocka ,  Jan Gray

Inventor： Martin Taillefer ,  Ali-Reza Adl-Tabatabai ,  Gad Sheaffer ,  Peter Lachner ,  Richard Wurdack ,  Darek Mihocka ,  Jan Gray

IPC: G06F9/44 ,  G06F15/76

CPC classification number: G06F11/362 ,  G06F12/0817

Abstract: Debugging software in systems with architecturally significant processor caches. A method may be practiced in a computing environment. The method includes acts for debugging a software application, wherein the software application is configured to use one or more architecturally significant processor caches coupled to a processor. The method includes beginning execution of the software application. A debugger is run while executing the software application. The software application causes at least one of reads or writes to be made to the cache in an architecturally significant fashion. The reads or writes made to the cache in an architecturally significant fashion are preserved while performing debugging operations that would ordinarily disturb the reads or writes made to the cache in an architecturally significant fashion.

Abstract translation: 在具有架构上重要的处理器高速缓存的系统中调试软件。 可以在计算环境中实施一种方法。 该方法包括用于调试软件应用程序的动作，其中软件应用被配置为使用耦合到处理器的一个或多个架构上重要的处理器高速缓存。 该方法包括开始执行软件应用程序。 在执行软件应用程序时运行调试器。 软件应用程序使得以架构上显着的方式对缓存进行读取或写入中的至少一个。 以架构上显着的方式对高速缓存进行的读取或写入被保留，同时执行调整操作，这些调试操作通常会以建筑上重要的方式干扰对高速缓存的读取或写入。