公开(公告)号：US20100075495A1

公开(公告)日：2010-03-25

申请号：US12237402

申请日：2008-09-25

Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Yu-Te Lu

Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Yu-Te Lu

IPC: H01L21/44

CPC classification number: H05K3/205 ,  H05K3/244 ,  H05K3/4647 ,  H05K2203/0361

Abstract: A method of selectively plating without plating lines is provided. The method employs a loading plate having a metalized temporary conductive layer. The loading plate and the temporary conductive layer are adapted for transmitting a plating current. A patterning photoresist layer is accorded for selectively and sequentially plating a separating metal layer, a plating protection layer, and a connection pad layer on to the temporary conductive layer. Then, the loading plate is further used for supplying current to form other circuit layers by a pressing lamination process. And when the plate process is completed or it is not need to plate, the loading plate and the temporary conductive layer can be removed, for further completing for example the solder mask process, and thus achieving the objective of plating without plating lines.

Abstract translation: 提供了一种选择性地镀覆电镀线的方法。 该方法采用具有金属化的临时导电层的装载板。 装载板和临时导电层适于传输电镀电流。 符合图案化光刻胶层的选择性和顺序地将分离金属层，电镀保护层和连接焊盘层电镀到临时导电层上。 然后，通过加压层压工艺，装载板还用于供给电流以形成其它电路层。 并且，当平板工艺完成或不需要平板化时，可以去除装载板和临时导电层，以进一步完成例如焊接掩模工艺，从而实现不镀覆线的电镀目的。

公开(公告)号：US20090001603A1

公开(公告)日：2009-01-01

申请号：US11772208

申请日：2007-06-30

Applicant: Chien-Wei Chang ,  Ting-Hao Lin

Inventor： Chien-Wei Chang ,  Ting-Hao Lin

IPC: H01L23/52 ,  H01L21/00

CPC classification number: H01L21/4846 ,  H01L21/565 ,  H01L21/6835 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81001 ,  H01L2224/81801 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/181 ,  H05K1/186 ,  H05K3/205 ,  H05K2201/10515 ,  H05K2201/10674 ,  H05K2203/049 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A high-density fine line structure mainly includes: two boards with similar structures and a dielectric film for combing the two boards. Semiconductor devices respectively in two boards are opposite to each other after the two boards are combined. The two boards each include a fine line circuit, an insulated layer on the same surface, and the semiconductor device installed above the fine line circuit. The surface of the circuit, which is not covered by a solder mask, is made into a pad. The pad is filled with the tin balls for electrically connecting with another semiconductor device. Electroplating rather than the etching method is used for forming the fine line circuit layer, and a carrier and a metal barrier layer, which are needed during or at the end of the manufacturing process, are removed to increase the wiring density for realizing the object of high-density.

公开(公告)号：US20090001547A1

公开(公告)日：2009-01-01

申请号：US11772219

申请日：2007-06-30

Applicant: Chien-Wei Chang ,  Ting-Hao Lin

Inventor： Chien-Wei Chang ,  Ting-Hao Lin

IPC: H01L23/48 ,  H01L21/58

CPC classification number: H01L21/6835 ,  H01L21/4846 ,  H01L23/3135 ,  H01L24/48 ,  H01L24/81 ,  H01L24/85 ,  H01L25/03 ,  H01L2221/68345 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A high-density fine line structure mainly includes: two packaged semiconductor devices installed on a circuit layer and a power/ground layer formed therebetween, to realize the objective of high-density and ground connection. On an outer circuit, the part, which is not covered by a solder mask, can be made into a pad for electrically connecting with one of the semiconductor devices. The other semiconductor device may be installed on the fine line circuit layer. The fine line circuit layer, which is exposed, is to be a tin ball pad where a tin ball is filled. Electroplating rather than the etching method is used for forming the fine line circuit layer, and a carrier and a metal barrier layer, which are needed during or at the end of the manufacturing process, are removed to increase the wiring density for realizing the object of high-density.

Abstract translation: 高密度细线结构主要包括：安装在电路层上的两个封装半导体器件和形成在其间的电源/接地层，以实现高密度和接地连接的目的。 在外部电路上，未被焊接掩模覆盖的部分可以制成用于与半导体器件中的一个电连接的焊盘。 另一个半导体器件可以安装在细线电路层上。 暴露的细线电路层是填充锡球的锡球垫。 使用电镀而不是蚀刻方法来形成细线电路层，并且去除在制造过程期间或结束时需要的载体和金属阻挡层，以增加用于实现该目的的物体的布线密度 高密度。

公开(公告)号：US20080070012A1

公开(公告)日：2008-03-20

申请号：US11523840

申请日：2006-09-20

Applicant: Li-Wei Kuo ,  Ting-Hao Lin

Inventor： Li-Wei Kuo ,  Ting-Hao Lin

IPC: B32B3/00

CPC classification number: H05K3/44 ,  H05K1/0206 ,  H05K1/056 ,  H05K3/062 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/10106 ,  H05K2203/0323 ,  Y10T428/24917

Abstract: A carrier board has a copper substrate, an insulating layer, a copper layer, multiple recesses and a metal circuit layer. The substrate has at least one through hole. The insulating layer is a layer of glue that is insulating, acid-resisting and high-temperature-resisting and is mounted in the at least one through hole and mounted on the substrate. The copper layer is mounted on the insulating layer. The recesses are formed in the copper layer and the insulating layer that is mounted on the substrate. The metal circuit layer is plated on copper layer and along the recesses to contact with the substrate. A heat from the metal circuit layer will transmit to the insulating layer by the copper layer and to the copper substrate. Thus, the carrier board has a heat-dissipating effect without combining with a dissipating apparatus, so LEDs packaged with the carrier board have a small dimension and are compact.

Abstract translation: 载体板具有铜基板，绝缘层，铜层，多个凹部和金属电路层。 基板具有至少一个通孔。 绝缘层是绝缘，耐酸和耐高温的胶层，并且安装在至少一个通孔中并安装在基板上。 铜层安装在绝缘层上。 凹部形成在铜层和安装在基板上的绝缘层上。 金属电路层镀在铜层上并沿着凹槽与衬底接触。 来自金属电路层的热量将通过铜层和铜基底传递到绝缘层。 因此，载板在不与耗散装置组合的情况下具有散热效果，因此与承载板封装的LED具有小尺寸并且紧凑。

公开(公告)号：US08161639B2

公开(公告)日：2012-04-24

申请号：US12895824

申请日：2010-09-30

Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Yu-Te Lu

Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Yu-Te Lu

IPC: H01K3/10

CPC classification number: H05K3/4679 ,  H05K1/0269 ,  H05K3/0035 ,  H05K3/421 ,  H05K3/4658 ,  H05K2201/09918 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method for fabricating an interlayer conducting structure of an embedded circuitry is disclosed. In accordance with the method for fabricating an interlayer conducting structure of an embedded circuitry of the present invention, there is no laser conformal mask formed prior to laminating the first and second lamination plates. Instead, after the first and second lamination plates are laminated, a laser boring process is directly conducted to form a via hole. In such a way, even when there is an offset between the first and the second lamination plates in alignment, the risk of short circuit between different layers of lamination plates can be lowered without improving an interlayer offset value.

Abstract translation: 公开了一种用于制造嵌入式电路的层间导电结构的方法。 根据本发明的嵌入式电路的层间导电结构的制造方法，在层叠第一和第二层压板之前不形成激光共形掩模。 相反，在第一和第二层压板层压之后，直接进行激光钻孔工艺以形成通孔。 以这种方式，即使在第一和第二层压板之间存在偏移对准的情况下，也可以在不改善层间偏移值的情况下降低层压板的不同层之间短路的风险。

公开(公告)号：US08051558B2

公开(公告)日：2011-11-08

申请号：US12329584

申请日：2008-12-06

Applicant: Ting-Hao Lin ,  Chien-Wei Chang

Inventor： Ting-Hao Lin ,  Chien-Wei Chang

IPC: H05K3/02 ,  H05K3/10

CPC classification number: H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/108 ,  H05K3/205 ,  H05K2201/09236 ,  H05K2201/09881 ,  Y10T29/49002 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/49155

Abstract: A manufacturing method for mainly embedding the passive device structure in the printed circuit board is presented. In this structure, both the source electrode and the ground electrode of the passive device belong to the same level, and includes several source branches and several ground branches that are formed vertically on the inside of the dielectric layer of the circuit board which are connected, respectively, to avoid the conducting between the source electrode and the ground electrode during lamination. When it is in the form of the capacitor structure, through the use of the ultra-fine wiring technique, these source branches and ground branches are separated by a small gap between each other. Therefore, the side face area and quantities of the source branches and ground branches are both increased.

Abstract translation: 提出了一种主要将无源器件结构嵌入印刷电路板的制造方法。 在该结构中，无源器件的源电极和接地电极都属于同一水平，并且包括垂直形成在电路板的电介质层的内部上的数个源极分支和几个接地分支， 以避免在层压期间源电极和接地电极之间的导电。 当它是电容器结构的形式时，通过使用超细布线技术，这些源极分支和接地分支之间彼此间有很小的间隙。 因此，源分支和接地分支的侧面积和数量都增加。

公开(公告)号：US20110083323A1

公开(公告)日：2011-04-14

申请号：US12895824

申请日：2010-09-30

Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Yu-Te Lu

Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Yu-Te Lu

IPC: H05K3/00

CPC classification number: H05K3/4679 ,  H05K1/0269 ,  H05K3/0035 ,  H05K3/421 ,  H05K3/4658 ,  H05K2201/09918 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method for fabricating an interlayer conducting structure of an embedded circuitry is disclosed. In accordance with the method for fabricating an interlayer conducting structure of an embedded circuitry of the present invention, there is no laser conformal mask formed prior to laminating the first and second lamination plates. Instead, after the first and second lamination plates are laminated, a laser boring process is directly conducted to form a via hole. In such a way, even when there is an offset between the first and the second lamination plates in alignment, the risk of short circuit between different layers of lamination plates can be lowered without improving an interlayer offset value.

Abstract translation: 公开了一种用于制造嵌入式电路的层间导电结构的方法。 根据本发明的嵌入式电路的层间导电结构的制造方法，在层叠第一和第二层压板之前不形成激光共形掩模。 相反，在第一和第二层压板层压之后，直接进行激光钻孔工艺以形成通孔。 以这种方式，即使在第一和第二层压板之间存在偏移对准的情况下，也可以在不改善层间偏移值的情况下降低层压板的不同层之间短路的风险。

公开(公告)号：US20100309608A1

公开(公告)日：2010-12-09

申请号：US12479810

申请日：2009-06-07

Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen ,  Yu-Te Lu

Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen ,  Yu-Te Lu

IPC: H01M6/14

CPC classification number: H01G4/01 ,  H01G4/005 ,  H01G4/06 ,  H01G4/228

Abstract: A buried capacitor structure including a first conductive metal layer, a first dielectric film, a capacitor, a second dielectric film, and a second conductive metal layer, which are stacked in sequence, wherein the capacitor is buried between the first dielectric film and the second dielectric film, the first conductive metal layer is formed into a first circuit pattern, the second conductive metal layer is formed into a second circuit pattern. The capacitor is a planar comb-shaped capacitor with a positive electrode, a negative electrode, and a capacitor paste filled between the positive electrode and the negative electrode, wherein the positive electrode includes a positive electrode end and a plurality of positive comb branches, the negative electrode includes a negative electrode end and a plurality of negative comb branches, and the positive branches and the negative branches are parallel to and separated from each other.

Abstract translation: 一种埋置电容器结构，其包括依次层叠的第一导电金属层，第一电介质膜，电容器，第二电介质膜和第二导电金属层，其中，所述电容器埋设在所述第一电介质膜和所述第二电介质膜之间 电介质膜，第一导电金属层形成为第一电路图案，第二导电金属层形成第二电路图案。 电容器是具有正极，负极和填充在正极和负极之间的电容器浆料的平面梳状电容器，其中正极包括正极端和多个正梳分支， 负极包括负极端和多个负梳分支，并且正分支和负分支彼此平行并分离。

公开(公告)号：US20100283145A1

公开(公告)日：2010-11-11

申请号：US12435409

申请日：2009-05-05

Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Yu-Te Lu ,  Wen-Chun Huang

Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Yu-Te Lu ,  Wen-Chun Huang

IPC: H01L23/498

CPC classification number: H01L23/49811 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/3841 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A stack structure with copper bumps on an integrated circuit board is disclosed. The stack structure includes a plurality of insulating layers and a plurality of conductive layers which are stacked alternately. The uppermost conductive layer has copper bumps as copper pillar pins for soldering the chip pins of an integrated circuit chip. Because the copper bumps have a certain height, the distance between the copper bumps and the chip pins is shortened, and therefore the solders needed for soldering may be reduced. Also, the shape of the solders is a long strap instead of spheroid due to the cohesion force between the copper bump surfaces and the solders so that the distance between the solders is scaled down and the gaps between the pins are reduced. Thus, the entire size of the integrated circuit board may also be miniatured.

Abstract translation: 公开了一种在集成电路板上具有铜凸块的堆叠结构。 堆叠结构包括交替堆叠的多个绝缘层和多个导电层。 最上层的导电层具有作为用于焊接集成电路芯片的芯片引脚的铜柱引脚的铜凸块。 由于铜凸块具有一定的高度，所以铜凸块和芯片销之间的距离缩短，因此焊接所需的焊料可能会降低。 此外，由于铜凸块表面和焊料之间的内聚力，焊料的形状是长带而不是球体，使得焊料之间的距离被缩小，并且销之间的间隙减小。 因此，集成电路板的整体尺寸也可以是微型的。

公开(公告)号：US20090294052A1

公开(公告)日：2009-12-03

申请号：US12131932

申请日：2008-06-03

Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Tu-Te Lu

Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Tu-Te Lu

IPC: B32B37/00

CPC classification number: B32B37/226 ,  B32B38/06 ,  B32B2305/342 ,  B32B2457/08 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/83005 ,  H01L2224/83132 ,  H05K1/023 ,  H05K1/185 ,  H05K1/188 ,  H05K3/025 ,  H05K2201/0355 ,  H05K2201/10636 ,  H05K2203/063 ,  Y02P70/611

Abstract: A method for fabricating a component-embedded PCB includes: providing a carrier plate having a plating metal layer plated thereon; disposing an electronic component on the plating metal layer of the carrier plate; laminating a metal layer onto the plating metal layer having the electronic component disposed thereon and the carrier plate by a dielectric film; removing the carrier plate and exposing the plating metal layer; and patterning at least one of the metal layer and the plating metal layer to be a circuit layer.

Abstract translation: 一种用于制造部件嵌入式PCB的方法包括：提供其上镀有电镀金属层的载体板; 将电子部件设置在载体板的电镀金属层上; 通过电介质膜将金属层层叠在其上设置有电子部件的电镀金属层和载体板上; 移除载体板并暴露电镀金属层; 并且将金属层和电镀金属层中的至少一个图案化为电路层。