公开(公告)号：US08288246B2

公开(公告)日：2012-10-16

申请号：US13018451

申请日：2011-02-01

Applicant: Chih-kuang Yang

Inventor： Chih-kuang Yang

IPC: H01L21/304

CPC classification number: H01L21/6835 ,  H01L27/1214 ,  H01L27/1266 ,  H01L2221/6835 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/00

Abstract: The present invention provides a structure combining an IC integrated substrate and a carrier, which comprises a carrier and an IC integrated substrate formed on the carrier. The IC integrated substrate has a first dielectric layer attached to the carrier. The materials of the carrier and the first dielectric layer are selected to prevent the IC integrated substrate from peeling off the carrier during processing and to allow the IC integrated substrate to naturally separate from the carrier after being cut, through the adhesion between the carrier and the first dielectric layer. The present invention also provides a method of manufacturing the above structure and a method of manufacturing electrical devices using the above structure.

Abstract translation: 本发明提供一种结合IC集成基板和载体的结构，其包括载体和形成在载体上的IC集成基板。 IC集成基板具有附接到载体的第一介电层。 选择载体和第一介电层的材料以防止IC集成基板在加工过程中从载体上剥离，并且通过载体和载体之间的粘附使IC集成基板在被切割后自然地与载体分离 第一电介质层。 本发明还提供一种制造上述结构的方法和使用上述结构制造电气装置的方法。

公开(公告)号：US08111519B2

公开(公告)日：2012-02-07

申请号：US13015725

申请日：2011-01-28

Applicant: Chih-kuang Yang

Inventor： Chih-kuang Yang

IPC: H05K7/00

CPC classification number: H05K1/147 ,  H01L23/13 ,  H01L23/5385 ,  H01L25/162 ,  H01L2224/48091 ,  H01L2924/01322 ,  H01L2924/19107 ,  H05K1/142 ,  H05K3/4611 ,  H05K2201/058 ,  H05K2201/091 ,  H05K2201/09109 ,  H05K2201/0919 ,  H05K2201/09481 ,  Y10T29/417 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T428/24322 ,  Y10T428/24917 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A hybrid structure of multi-layer substrates comprises a first multi-layer substrate and a second multi-layer substrate. The first multi-layer substrate stacks up first metal layers, first dielectric layers alternately and has VIAs. A border district of a first metal layer connects with a border district of the corresponding first dielectric layer. The border districts are separated from adjacent first metal layers and adjacent first dielectric layers. The second multi-layer substrate stacks up second metal layers and second dielectric layers alternately. A border district of a second metal layer connects with a border district of the corresponding second dielectric layer. The border districts are separated from adjacent second metal layers and adjacent second dielectric layers. The VIAs are located at the border districts of the first dielectric layers and each VIA has electric conductor therein to connect one first metal layer with one second metal layer.

Abstract translation: 多层基板的混合结构包括第一多层基板和第二多层基板。 第一多层基板交替地堆叠第一金属层，第一介电层并具有VIA。 第一金属层的边界区域与相应的第一介电层的边界区域连接。 边界区域与相邻的第一金属层和相邻的第一介电层分离。 第二多层基板交替堆叠第二金属层和第二电介质层。 第二金属层的边界区域与相应的第二电介质层的边界区域连接。 边界区域与相邻的第二金属层和相邻的第二介电层分离。 VIA位于第一电介质层的边界区，并且每个VIA具有导电体，以将一个第一金属层与一个第二金属层连接。

公开(公告)号：US20110212307A1

公开(公告)日：2011-09-01

申请号：US13104293

申请日：2011-05-10

Applicant: Chih-kuang Yang

Inventor： Chih-kuang Yang

IPC: B32B3/00

CPC classification number: H05K1/0271 ,  H05K3/4611 ,  H05K2201/09136 ,  H05K2201/09781 ,  Y10T428/24752

Abstract: Disclosed is a method to decrease warpage of a multi-layer substrate, comprises a plurality of metal layers and a plurality of dielectric layers, which are alternately formed. A plane parallel with a first metal layer and a second metal layer of the plurality of metal layers substantially has the same distance between the first metal layer and the second metal layer respectively. The plane is defined as a central plane between the first metal layer and the second metal layer. A first total area covered by metal in the first metal layer is larger than a second area covered by metal in the second metal layer. At least one redundant metal is further set in same layer of the second metal layer. A second total area comprising a redundant metal area covered by the redundant metal and the second area is considerably equivalent to the first total area.

Abstract translation: 公开了减少多层基板的翘曲的方法，包括交替形成的多个金属层和多个电介质层。 平行于多个金属层的第一金属层和第二金属层的平面基本上在第一金属层和第二金属层之间具有相同的距离。 平面被定义为第一金属层和第二金属层之间的中心平面。 在第一金属层中由金属覆盖的第一总面积大于在第二金属层中由金属覆盖的第二区域。 至少一个冗余金属被进一步设置在第二金属层的相同层中。 包括由冗余金属和第二区域覆盖的冗余金属区域的第二总面积与第一总区域相当。

公开(公告)号：US20110212257A1

公开(公告)日：2011-09-01

申请号：US13106376

申请日：2011-05-12

Applicant: Chih-kuang Yang

Inventor： Chih-kuang Yang

IPC: B05D5/12

CPC classification number: H05K1/0271 ,  H05K3/4611 ,  H05K2201/09136 ,  H05K2201/09781

Abstract: Disclosed is a method to improve heat dissipation efficiency and to decrease warpage of a multi-layer substrate, comprising a plurality of metal layers and a plurality of dielectric layers, which are alternately formed. A plane parallel with a first metal layer and a second metal layer, substantially has the same distance between the first metal layer and the second metal layer respectively. The plane is defined as a central plane between the first metal layer and the second metal layer. A first total area covered by metal in the first metal layer is larger than a second area covered by metal in the second metal layer. At least one redundant metal is set in same layer of the second metal layer to make a second total area comprising a redundant metal area covered by the redundant metal and the second area considerably equivalent to the first total area.

Abstract translation: 公开了一种提高散热效率并降低多层基板的翘曲的方法，该多层基板包括交替形成的多个金属层和多个电介质层。 平行于第一金属层和第二金属层的平面在第一金属层和第二金属层之间基本上具有相同的距离。 平面被定义为第一金属层和第二金属层之间的中心平面。 在第一金属层中由金属覆盖的第一总面积大于在第二金属层中由金属覆盖的第二区域。 将至少一个冗余金属设置在第二金属层的相同层中，以形成第二总面积，其包括由冗余金属覆盖的冗余金属区域和与第一总区域相当的第二区域。

公开(公告)号：US20100104889A1

公开(公告)日：2010-04-29

申请号：US12651866

申请日：2010-01-04

Applicant: Chih-kuang Yang

Inventor： Chih-kuang Yang

IPC: B32B15/01

CPC classification number: B32B3/04 ,  B32B7/02 ,  B32B15/00 ,  H05K1/0271 ,  H05K3/4611 ,  H05K2201/09136 ,  H05K2201/09781 ,  Y10T428/12493 ,  Y10T428/24917

Abstract: Disclosed is a method to decrease warpage of a multi-layer substrate, comprises a first metal layer and a second metal layer. First area of the first metal layer is larger than second area of the second metal layer. In the same layer of the second metal layer, a redundant metal layer can be set to make a redundant metal layer area plus the second area considerably equivalent to the first area. Alternatively, a redundant space can be set in the first metal layer to achieve the same result. When the multi-layer substrate comprises a first dielectric layer with an opening and a second dielectric layer, a redundant opening positioned corresponding to the opening can be set in the second dielectric layer. The present invention employs a method of balancing the multi-layer substrate stress, i.e. to homogenize the multi-layer structure composed of different metal layers and dielectric layers to decrease warpage thereof.

Abstract translation: 公开了减少多层基板翘曲的方法，包括第一金属层和第二金属层。 第一金属层的第一区域大于第二金属层的第二区域。 在第二金属层的相同层中，可以设置冗余金属层以形成与第一区域大致相当的冗余金属层区域加上第二区域。 或者，可以在第一金属层中设置冗余空间以获得相同的结果。 当多层基板包括具有开口的第一电介质层和第二电介质层时，可以在第二电介质层中设置对应于开口的冗余开口。 本发明采用平衡多层基板应力的方法，即均匀化由不同金属层和电介质层组成的多层结构，以减少其翘曲。

公开(公告)号：US20090181496A1

公开(公告)日：2009-07-16

申请号：US12255770

申请日：2008-10-22

Applicant: Chih-kuang Yang

Inventor： Chih-kuang Yang

IPC: H01L21/00

CPC classification number: H05K3/20 ,  H01L24/16 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2924/00014 ,  H01L2924/14 ,  H05K1/111 ,  H05K3/3452 ,  H05K2201/10674 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: Disclosed are a multi-layer substrate and a manufacture method thereof. The multi-layer substrate of the present invention comprises a surface dielectric layer and at least one bond pad layer. The surface dielectric layer is located at a surface of the multi-layer substrate. The bond pad layer is embedded in the surface dielectric layer to construct the multi-layer substrate with the surface dielectric layer of the present invention. The manufacture method of the present invention forms at least one bond pad layer on a flat surface of a carrier and then forms the surface dielectric layer to cover the bond pad layer where the bond pad layer is embedded therein. After the multi-layer substrate is separated from the carrier, the bond pad layer and the surface dielectric layer construct a flat surface of the multi-layer substrate.

Abstract translation: 公开了一种多层基板及其制造方法。 本发明的多层基板包括表面介电层和至少一个接合焊盘层。 表面介电层位于多层基板的表面。 接合焊盘层嵌入在表面电介质层中以构成具有本发明的表面电介质层的多层基板。 本发明的制造方法在载体的平坦表面上形成至少一个接合焊盘层，然后形成表面电介质层以覆盖键合焊盘层，其中嵌入焊盘层。 在多层基板与载体分离之后，接合焊盘层和表面电介质层构成多层基板的平坦表面。

公开(公告)号：US20080289863A1

公开(公告)日：2008-11-27

申请号：US11950816

申请日：2007-12-05

Applicant: Chih-kuang Yang ,  Chieh-lin Hsing

Inventor： Chih-kuang Yang ,  Chieh-lin Hsing

IPC: H05K1/09 ,  H05K3/00

CPC classification number: H05K3/4007 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K3/205 ,  H05K3/243 ,  H05K3/3452 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/099 ,  Y10T29/49126 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A surface finish structure of multi-layer substrate and manufacturing method thereof. The surface finish structure of the present invention includes a bond pad layer, at least one cover metal layer and a solder mask. The cover metal layer covers the bond pad layer. The solder mask has a hole to expose the cover metal layer. The present invention can form the cover metal layer to cover the bond pad layer and then forms the solder mask. Thereafter, the hole is made to the solder mask at the position of the cover metal layer to expose thereof. Because the bond pad layer is embedded in a dielectric layer of the multi-layer substrate, adhesion intensity between the bond pad layer and the dielectric layer can be enhanced. Meanwhile, contact of the bond pad layer with the solder can be prevented with the cover metal layer.

Abstract translation: 多层基板的表面处理结构及其制造方法。 本发明的表面光洁度结构包括接合焊盘层，至少一个覆盖金属层和焊接掩模。 覆盖金属层覆盖接合焊盘层。 焊接掩模具有用于露出覆盖金属层的孔。 本发明可以形成覆盖金属层以覆盖接合焊盘层，然后形成焊料掩模。 此后，在覆盖金属层的位置处将该孔制成焊料掩模以使其露出。 由于接合焊盘层嵌入在多层基板的电介质层中，所以可以提高接合焊盘层与电介质层之间的粘合强度。 同时，可以通过覆盖金属层来防止接合焊盘层与焊料的接触。