公开(公告)号：US10037946B2

公开(公告)日：2018-07-31

申请号：US15796856

申请日：2017-10-30

Applicant: Dyi-Chung Hu

Inventor： Dyi-Chung Hu

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L21/48 ,  H01L25/00

CPC classification number: H01L23/5386 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/03 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/023 ,  H01L2224/0401 ,  H01L2224/1403 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161

Abstract: A package structure having an embedded bonding film including a redistribution substrate, a bonding film and a core is provided. The redistribution substrate has a top side and a bottom side opposite to the top side. The bonding film disposed at the top side and embedded in the redistribution substrate includes at least one bonding area and a metal circuit is disposed within the bonding area. The bonding area includes an outer top metal pad electrically coupled to an outer end of the metal circuit and an inner top metal pad on a top surface of the bonding film within the bonding area and electrically coupled to an inner end of the metal circuit. The core disposed at the bottom side of the redistribution substrate and electrically coupled to the redistribution substrate. A Young's modulus of the core is greater than a Young's modulus of the redistribution substrate.

公开(公告)号：US09859202B2

公开(公告)日：2018-01-02

申请号：US15190695

申请日：2016-06-23

Applicant: Dyi-Chung Hu

Inventor： Dyi-Chung Hu

IPC: H05K1/11 ,  H01L23/498 ,  H01L21/48 ,  H01L25/10

CPC classification number: H01L23/49838 ,  H01L21/4846 ,  H01L21/486 ,  H01L23/49827 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/15313 ,  H01L2924/15331

Abstract: A fabricating process for a spacer connector is disclosed. A core substrate with a plurality of through holes is prepared. A conductive carrier with a dielectric adhesive configured on a top surface is prepared. The core substrate is then pasted on a top surface of the dielectric adhesive layer. The dielectric adhesive exposed in the through hole is then etched. An electric plating process to form metal pillar in the core substrate is performed using the conductive carrier as one of the electrode.

公开(公告)号：US09799622B2

公开(公告)日：2017-10-24

申请号：US14509395

申请日：2014-10-08

Applicant: Dyi-Chung Hu

Inventor： Dyi-Chung Hu

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L21/78 ,  H01L23/28 ,  H05K1/11 ,  H01L21/683 ,  H01L23/31 ,  H01L21/56 ,  H01L25/065

CPC classification number: H01L24/25 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/28 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5385 ,  H01L24/14 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L25/0655 ,  H01L2221/68345 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2224/97 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/15788 ,  H01L2924/18161 ,  H05K1/111 ,  H01L2224/81

Abstract: The present invention discloses a high density film for IC package. The process comprises: a redistribution layer is fabricated following IC design rule, with a plurality of bottom pad formed on bottom, and with a plurality of first top pad formed on top; wherein the density of the plurality of bottom pad is higher than the density of the plurality of first top pad; and a top redistribution layer is fabricated following PCB design rule, using the plurality of the first top pad as a starting point; with a plurality of second top pad formed on top; wherein a density of the plurality of first top pad is higher than a density of the plurality of second top pad.

公开(公告)号：US09735079B2

公开(公告)日：2017-08-15

申请号：US14878302

申请日：2015-10-08

Applicant: Dyi-Chung Hu

Inventor： Dyi-Chung Hu

IPC: H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L23/14

CPC classification number: H01L23/3157 ,  H01L23/145 ,  H01L23/31 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/562 ,  H01L24/17 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2924/15192 ,  H01L2924/15311

Abstract: A package substrate for chip/chips package wrapped by a molding compound is disclosed. The molding compound functions as a stiffener for the thin film package substrate. One embodiment discloses at least one redistribution layer (RDL) is prepared and the RDL is wrapped by a molding compound. The molding compound wraps four lateral sides and bottom side of the RDL. A top side of the RDL is made for a chip to mount and a bottom side of the RDL is planted a plurality of solder balls so that the bottom side of the chip package is adaptive to mount onto a system board in a later process.

公开(公告)号：US09691717B2

公开(公告)日：2017-06-27

申请号：US15264757

申请日：2016-09-14

Applicant: Dyi-Chung Hu

Inventor： Dyi-Chung Hu

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L21/78 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/561 ,  H01L21/563 ,  H01L21/566 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2224/83

Abstract: A core substrate is prepared first, a bottom redistribution layer RDL1 is formed. Any warpage of the RDL1 is suppressed by the core substrate. In a later process, warpage is further suppressed by a molding compound encapsulating the core substrate. A plurality of metal pillars are formed passing through the core substrate longitudinally; a top redistribution layer RDL2 is then formed on a top surface of the metal pillars.

公开(公告)号：US09685429B2

公开(公告)日：2017-06-20

申请号：US14671623

申请日：2015-03-27

Applicant: Dyi-Chung Hu

Inventor： Dyi-Chung Hu

IPC: H01L25/18 ,  H01L25/10 ,  H05K1/14 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/18 ,  H01L23/49811 ,  H01L24/13 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/81447 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H05K1/14 ,  H05K1/144 ,  H05K3/3436 ,  H05K3/4007 ,  H05K2201/042 ,  H05K2201/10159 ,  H01L2924/00014 ,  H01L2924/014

Abstract: 3D Stacked memory devices with copper pillars electrically connecting the package units are disclosed. A stacked package-on-package memory device includes a base chip package unit having a logic processing chip disposed on a base substrate; and a memory chip stack overlying the base chip unit. The memory chip stack includes a stack of packaged memory units. Each packaged memory unit including a memory chip on an IC substrate. Copper pillars are disposed on the back side of the IC substrate and electrically connected to the base substrate.

公开(公告)号：US09673148B2

公开(公告)日：2017-06-06

申请号：US14931044

申请日：2015-11-03

Applicant: Dyi-Chung Hu

Inventor： Dyi-Chung Hu

IPC: H01L23/48 ,  H01L23/538 ,  H01L23/31 ,  H01L23/522 ,  H01L21/56 ,  H01L23/532 ,  H01L25/16 ,  H01L21/768

CPC classification number: H01L25/50 ,  H01L21/565 ,  H01L21/568 ,  H01L21/768 ,  H01L23/3114 ,  H01L23/49805 ,  H01L23/49866 ,  H01L23/5226 ,  H01L23/53242 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/16 ,  H01L2224/02311 ,  H01L2224/02331 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043

Abstract: An electronic system without using solder balls between electrical components, and without using interposer between chips and package substrate, without using a discrete system board for the chip package to mount. A chip is wrapped by molding material, a first redistribution circuitry is built on a bottom side of the molding material; a second redistribution circuitry is built on a bottom side of the first redistribution circuitry. A third redistribution circuitry is built on a bottom side of the second redistribution circuitry. Plated metal vias are configured between each two of the electrical components.

公开(公告)号：US08304923B2

公开(公告)日：2012-11-06

申请号：US11692933

申请日：2007-03-29

Applicant: Dyi-Chung Hu ,  Yu-Shan Hu ,  Chih-Wei Lin

Inventor： Dyi-Chung Hu ,  Yu-Shan Hu ,  Chih-Wei Lin

IPC: H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L23/28

CPC classification number: H01L23/3128 ,  H01L21/6835 ,  H01L24/28 ,  H01L24/32 ,  H01L25/105 ,  H01L25/50 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14683 ,  H01L2224/32057 ,  H01L2224/83194 ,  H01L2224/83385 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/078 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/16195 ,  H01L2924/1815 ,  H01L2924/01026 ,  H01L2924/01028

Abstract: A chip packaging structure comprising a chip, a plurality of conductive pillars surrounding the chip, an encapsulation encapsulating the chip and the conductive pillars, and a connecting layer is provided. The encapsulation has a first side and a second side corresponding to the first side. The connecting layer is disposed at the first side of the encapsulation and electrically connected between the chip and the conductive pillars. Furthermore, a chip packaging process accompanying the chip packaging structure is also provided. The chip packaging structure is more useful and powerful and is suitable for various chip packaging applications, and the chip packaging process can reduce the manufacturing time and save the production cost.

Abstract translation: 一种芯片封装结构，包括芯片，围绕芯片的多个导电柱，封装芯片和导电柱的封装以及连接层。 封装具有对应于第一侧的第一侧和第二侧。 连接层设置在封装的第一侧并电连接在芯片和导电柱之间。 此外，还提供了伴随芯片封装结构的芯片封装工艺。 芯片封装结构更加实用，功能强大，适用于各种芯片封装应用，芯片封装工艺可以缩短制造时间，节省生产成本。

公开(公告)号：US20080073774A1

公开(公告)日：2008-03-27

申请号：US11566242

申请日：2006-12-04

Applicant: Wen-Kun Yang ,  Dyi-Chung Hu ,  Chih-Ming Chen ,  Hsien-Wen Hsu

Inventor： Wen-Kun Yang ,  Dyi-Chung Hu ,  Chih-Ming Chen ,  Hsien-Wen Hsu

IPC: H01L23/04

CPC classification number: H01L23/5389 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/19 ,  H01L24/82 ,  H01L24/97 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/12105 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01094 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A chip package including a multilayer substrate, an adhesive core layer and a chip is provided. The multilayer substrate has a plurality of material layers. The adhesive core layer is disposed on the multilayer substrate. The chip is disposed in the adhesive core layer. The chip has an active surface exposed outside the adhesive core layer. The chip includes a plurality of bonding pads disposed on the active surface and a plurality of metal conductive bodies electrically connected to the bonding pads respectively.

Abstract translation: 提供了包括多层基板，粘合芯层和芯片的芯片封装。 多层基板具有多个材料层。 粘合芯层设置在多层基板上。 芯片设置在粘合芯层中。 该芯片具有暴露在粘合芯层外的活性表面。 芯片包括设置在有源表面上的多个接合焊盘和分别与焊盘电连接的多个金属导电体。

公开(公告)号：US20050196902A1

公开(公告)日：2005-09-08

申请号：US10906681

申请日：2005-03-02

Applicant: Dyi-Chung Hu ,  Chih-Kung Huang ,  Chien-Nan Wu

Inventor： Dyi-Chung Hu ,  Chih-Kung Huang ,  Chien-Nan Wu

IPC: H01L21/4763 ,  H01L21/48 ,  H01L23/28 ,  H01L23/495 ,  H05K1/00 ,  H05K3/00 ,  H05K3/06 ,  H05K3/38 ,  H05K3/40

CPC classification number: H01L21/4839 ,  H01L23/49572 ,  H01L2924/0002 ,  H05K1/0393 ,  H05K3/002 ,  H05K3/0097 ,  H05K3/064 ,  H05K3/386 ,  H05K3/4092 ,  H05K2201/0166 ,  H05K2201/0397 ,  H05K2201/09063 ,  H05K2203/1545 ,  H01L2924/00

Abstract: A method of fabricating a film carrier. The method comprises the steps of providing a film; forming a plurality of sprocket holes in the film; forming a metallic layer on the film; patterning the film in an etching operation to form a plurality of openings; and, patterning the metallic layer to form a plurality of metallic leads.

Abstract translation: 一种制造薄膜载体的方法。 该方法包括提供薄膜的步骤; 在膜中形成多个链轮孔; 在膜上形成金属层; 在蚀刻操作中图案化膜以形成多个开口; 并且图案化金属层以形成多个金属引线。