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公开(公告)号：US20250110848A1
公开(公告)日：2025-04-03
申请号：US18395390
申请日：2023-12-22
Applicant: Intel Corporation
Inventor： Ahmad Yasin , Andreas Kleen , Jonathan Combs
IPC: G06F11/34
Abstract: Techniques for performance monitoring are described. In certain examples, an apparatus (e.g., a processor) includes an execution circuit to execute one or more instructions; a performance monitoring counter; a control register comprising a threshold field; and a performance monitor control circuit to increment the performance monitoring counter in response to a performance monitoring event of the one or more instructions being equal to, but not greater than, the threshold field.
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公开(公告)号：US12189509B2
公开(公告)日：2025-01-07
申请号：US18252659
申请日：2020-12-24
Applicant: Intel Corporation
Inventor： Wei Wang , Matthew Merten , Beeman Strong , Andreas Kleen , Kan Liang , Gilbert Neiger , Kun Tian , Like Xu
Abstract: In an embodiment, a processor for redirecting requests includes a processing engine to execute a guest system, and monitoring circuitry coupled to the processing engine. The monitoring circuitry may be to: receive, from the guest system, a first request to access a first virtual counter; in response to a receipt of the first request, determine, based a mapping register of the processor, a first physical counter mapped to the first virtual counter; and redirect the first request to the first physical counter mapped to the first virtual counter. Other embodiments are described and claimed.
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公开(公告)号：US11900115B2
公开(公告)日：2024-02-13
申请号：US18126920
申请日：2023-03-27
Applicant: Intel Corporation
Inventor： Ashok Raj , Andreas Kleen , Gilbert Neiger , Beeman Strong , Jason Brandt , Rupin Vakharwala , Jeff Huxel , Larisa Novakovsky , Ido Ouziel , Sarathy Jayakumar
CPC classification number: G06F9/30098 , G06F9/4812 , G06F9/5005 , G06F15/80
Abstract: An apparatus and method for processing non-maskable interrupt source information. For example, one embodiment of a processor comprises: a plurality of cores comprising execution circuitry to execute instructions and process data; local interrupt circuitry comprising a plurality of registers to store interrupt-related data including non-maskable interrupt (NMI) data related to a first NMI; and non-maskable interrupt (NMI) processing mode selection circuitry, responsive to a request, to select between at least two NMI processing modes to process the first NMI including: a first NMI processing mode in which the plurality of registers are to store first data related to a first NMI, wherein no NMI source information related to a source of the NMI is included in the first data, and a second NMI processing mode in which the plurality of registers are to store both the first data related to the first NMI and second data comprising NMI source information indicating the NMI source.
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公开(公告)号：US20240012735A1
公开(公告)日：2024-01-11
申请号：US18252659
申请日：2020-12-24
Applicant: Intel Corporation
Inventor： Wei Wang , Matthew Merten , Beeman Strong , Andreas Kleen , Kan Liang , Gilbert Neiger , Kun Tian , Like Xu
CPC classification number: G06F11/3466 , G06F11/0772 , G06F9/45545
Abstract: In an embodiment, a processor for redirecting requests includes a processing engine to execute a guest system, and monitoring circuitry coupled to the processing engine. The monitoring circuitry may be to: receive, from the guest system, a first request to access a first virtual counter; in response to a receipt of the first request, determine, based a mapping register of the processor, a first physical counter mapped to the first virtual counter; and redirect the first request to the first physical counter mapped to the first virtual counter. Other embodiments are described and claimed.
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35.发明公开公开(公告)号：US20240004659A1
公开(公告)日：2024-01-04
申请号：US17853087
申请日：2022-06-29
Applicant: Intel Corporation
Inventor： Michael LeMay , Dan Baum , Joseph Cihula , Joao Batista Correa Gomes Moreira , Anjo Lucas Vahldiek-Oberwagner , Scott Constable , Andreas Kleen , Konrad Lai , Henrique de Medeiros Kawakami , David M. Durham
IPC: G06F9/30
CPC classification number: G06F9/3016
Abstract: Techniques for an instruction for a Runtime Call operation are described. An example apparatus comprises decoder circuitry to decode a single instruction, the single instruction to include a field for an identifier of an opcode, the opcode to indicate execution circuitry is to execute a no operation when a runtime call destination equals a predetermined value; and execute an indirect call with the runtime call destination as a destination address when the runtime call destination does not equal the predetermined value. Other examples are described and claimed.
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Patent Agency Ranking
公开(公告)号：US11169929B2
公开(公告)日：2021-11-09
申请号：US15958591
申请日：2018-04-20
Applicant: Intel Corporation
Inventor： Rupin Vakharwala , Amin Firoozshahian , Stephen Van Doren , Rajesh Sankaran , Mahesh Madhav , Omid Azizi , Andreas Kleen , Mahesh Maddury , Ashok Raj
IPC: G06F12/1009 , G06F3/06 , G06F12/0862 , G06F9/38 , G06F12/1081 , G06F12/1045 , G06F12/1027
Abstract: A processing device includes a core to execute instructions, and memory management circuitry coupled to, memory, the core and an I/O device that supports page faults. The memory management circuitry includes an express invalidations circuitry, and a page translation permission circuitry. The memory management circuitry is to, while the core is executing the instructions, receive a command to pause communication between the I/O device and the memory. In response to receiving the command to pause the communication, modify permissions of page translations by the page translation permission circuitry and transmit an invalidation request, by the express invalidations circuitry to the I/O device, to cause cached page translations in the I/O device to be invalidated.
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公开(公告)号：US11048512B1
公开(公告)日：2021-06-29
申请号：US16833598
申请日：2020-03-28
Applicant: Intel Corporation
Inventor： Ashok Raj , Andreas Kleen , Gilbert Neiger , Beeman Strong , Jason Brandt , Rupin Vakharwala , Jeff Huxel , Larisa Novakovsky , Ido Ouziel , Sarathy Jayakumar
Abstract: An apparatus and method for processing non-maskable interrupt source information. For example, one embodiment of a processor comprises: a plurality of cores comprising execution circuitry to execute instructions and process data; local interrupt circuitry comprising a plurality of registers to store interrupt-related data including non-maskable interrupt (NMI) data related to a first NMI; and non-maskable interrupt (NMI) processing mode selection circuitry, responsive to a request, to select between at least two NMI processing modes to process the first NMI including: a first NMI processing mode in which the plurality of registers are to store first data related to a first NMI, wherein no NMI source information related to a source of the NMI is included in the first data, and a second NMI processing mode in which the plurality of registers are to store both the first data related to the first NMI and second data comprising NMI source information indicating the NMI source.
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公开(公告)号：US20200242003A1
公开(公告)日：2020-07-30
申请号：US16699871
申请日：2019-12-02
Applicant: Intel Corporation
Inventor： Matthew C. Merten , Beeman C. Strong , Michael W. Chynoweth , Grant G. Zhou , Andreas Kleen , Kimberly C. Weier , Angela D. Schmid , Stanislav Bratanov , Seth Abraham , Jason W. Brandt , Ahmad Yasin
Abstract: A processor is to execute and retire instructions for a virtual machine. A reload register is coupled to the core is to store a reload value. A performance monitoring counter (PMC) register is coupled to the reload register and an event-based sampler operatively is coupled to the reload register and the PMC register. The event-based sampler includes circuitry to load the reload value into the PMC register and increment the PMC register after detecting each occurrence of an event of a certain type as a result of execution of the instructions. Upon detecting an occurrence of the event after the PMC register reaches a predetermined trigger value, the event-based sampler is to execute microcode to generate field data for elements within a sampling record, wherein the field data relates to a current processor state of execution, and reload the reload value from the reload register into the PMC register.
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公开(公告)号：US10346300B2
公开(公告)日：2019-07-09
申请号：US15628811
申请日：2017-06-21
Applicant: Intel Corporation
Inventor： Avinash Sodani , Robert J. Kyanko , Richard J. Greco , Andreas Kleen , Milind B. Girkar , Christopher M. Cantalupo
Abstract: In one embodiment, a processor comprises: at least one core formed on a die to execute instructions; a first memory controller to interface with an in-package memory; a second memory controller to interface with a platform memory to couple to the processor; and the in-package memory located within a package of the processor, where the in-package memory is to be identified as a more distant memory with respect to the at least one core than the platform memory. Other embodiments are described and claimed.
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40.发明授权公开(公告)号：US10013335B2
公开(公告)日：2018-07-03
申请号：US14977071
申请日：2015-12-21
Applicant: Intel Corporation
Inventor： Andreas Kleen
CPC classification number: G06F11/3644 , G06F11/3466 , G06F11/3624 , G06F11/366 , G06F2201/865
Abstract: A program control flow trace is obtained from a processor trace module, which may be hardware based, and is used, in combination with debug information and information from dissassembly of basic blocks, to identify candidate store instruction(s) which produced a memory corruption. The candidate store instruction(s) and links to a software program may be used to further debug the memory corruption and/or to instrument the software program to identify basic block(s) which produced the memory corruption in future executions of the compiled software program and/or to track debugging of the software program.
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