公开(公告)号：US20230088578A1

公开(公告)日：2023-03-23

申请号：US17448385

申请日：2021-09-22

Applicant: INTEL CORPORATION

Inventor： Nicholas A. Thomson ,  Ayan Kar ,  Benjamin Orr ,  Kalyan C. Kolluru ,  Nathan D. Jack ,  Patrick Morrow ,  Cheng-Ying Huang ,  Charles C. Kuo

IPC: H01L27/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66 ,  H01L21/8238

Abstract: Integrated circuits including lateral diodes. In an example, diodes are formed with laterally neighboring source and drain regions (diffusion regions) configured with different polarity epitaxial growths (e.g., p-type and n-type), to provide an anode and cathode of the diode. In some such cases, dopants may be used in the channel region to create or otherwise enhance a PN or PIN junction between the diffusion regions and the semiconductor material of a channel region. The channel region can be, for instance, one or more nanoribbons or other such semiconductor bodies that extend between the oppositely-doped diffusion regions. In some cases, nanoribbons making up the channel region are left unreleased, thereby preserving greater volume through which diode current can flow. Other features include skipped epitaxial regions, elongated gate structures, using isolation structures in place of gate structures, and/or sub-fin conduction paths that are supplemental or alternative to a channel-based conduction paths.

公开(公告)号：US20230087444A1

公开(公告)日：2023-03-23

申请号：US17448384

申请日：2021-09-22

Applicant: INTEL CORPORATION

Inventor： Nicholas A. Thomson ,  Ayan Kar ,  Benjamin Orr ,  Kalyan C. Kolluru ,  Nathan D. Jack ,  Patrick Morrow ,  Cheng-Ying Huang ,  Charles C. Kuo

IPC: H01L27/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66 ,  H01L21/8238

Abstract: Integrated circuits including lateral diodes. In an example, diodes are formed with laterally neighboring source and drain regions (diffusion regions) configured with different polarity epitaxial growths (e.g., p-type and n-type), to provide an anode and cathode of the diode. In some such cases, dopants may be used in the channel region to create or otherwise enhance a PN or PIN junction between the diffusion regions and the semiconductor material of a channel region. The channel region can be, for instance, one or more nanoribbons or other such semiconductor bodies that extend between the oppositely-doped diffusion regions. In some cases, nanoribbons making up the channel region are left unreleased, thereby preserving greater volume through which diode current can flow. Other features include skipped epitaxial regions, elongated gate structures, using isolation structures in place of gate structures, and/or sub-fin conduction paths that are supplemental or alternative to a channel-based conduction path.

公开(公告)号：US10950660B2

公开(公告)日：2021-03-16

申请号：US16328533

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Kaan Oguz ,  Kevin P. OBrien ,  Brian S. Doyle ,  Charles C. Kuo ,  Mark L. Doczy

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L43/02

Abstract: A perpendicular spin transfer torque memory (pSTTM) device incorporates a magnetic tunnel junction (MTJ) device having a free magnetic stack and a fixed magnetic stack separated by a dielectric tunneling layer. The free magnetic stack includes an uppermost magnetic layer that is at least partially covered by a cap layer. The cap layer is at least partially covered by a protective layer containing at least one of: ruthenium (Ru); cobalt/iron/boron (CoFeB); molybdenum (Mo); cobalt (Co); tungsten (W); or platinum (Pt). The protective layer is at least partially covered by a cap metal layer which may form a portion of MTJ electrode. The protective layer minimizes the occurrence of physical and/or chemical attack of the cap layer by the materials used in the cap metal layer, beneficially improving the interface anisotropy of the MTJ free magnetic layer.

公开(公告)号：US10832847B2

公开(公告)日：2020-11-10

申请号：US15735622

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Brian S. Doyle ,  Kaan Oguz ,  Kevin P. O'Brien ,  David L. Kencke ,  Charles C. Kuo ,  Mark L. Doczy ,  Satyarth Suri ,  Robert S. Chau

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01F10/193 ,  H01F10/32

Abstract: An embodiment includes an apparatus comprising: a substrate; a magnetic tunnel junction (MTJ), on the substrate, comprising a fixed layer, a free layer, and a dielectric layer between the fixed and free layers; and a first synthetic anti-ferromagnetic (SAF) layer, a second SAF layer, and an intermediate layer, which includes a non-magnetic metal, between the first and second SAF layers; wherein the first SAF layer includes a Heusler alloy. Other embodiments are described herein.

公开(公告)号：US10832749B2

公开(公告)日：2020-11-10

申请号：US15735625

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Charles C. Kuo ,  Justin S. Brockman ,  Juan G. Alzate Vinasco ,  Kaan Oguz ,  Kevin P. O'Brien ,  Brian S. Doyle ,  Mark L. Doczy ,  Satyarth Suri ,  Robert S. Chau

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  G11C11/16

Abstract: An embodiment includes an apparatus including: a substrate; a perpendicular magnetic tunnel junction (pMTJ), on the substrate, including a first fixed layer, a second fixed layer, and a free layer between the first and second fixed layers; a first dielectric layer between the first fixed layer and the free layer; and a second layer between the second fixed layer and the free layer. Other embodiments are described herein.

公开(公告)号：US10580975B2

公开(公告)日：2020-03-03

申请号：US15753468

申请日：2015-09-18

Applicant: Intel Corporation

Inventor： Mark L. Doczy ,  Brian S. Doyle ,  Charles C. Kuo ,  Kaan Oguz ,  Kevin P. O'Brien ,  Satyarth Suri ,  Tejaswi K. Indukuri

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  G11C11/16 ,  H01F10/32 ,  H01F41/34 ,  H01L27/22

Abstract: Technologies for manufacturing spin transfer torque memory (STTM) elements are disclosed. In some embodiments, the technologies include methods for removing a re-deposited layer and/or interrupting the electrical continuity of a re-deposited layer that may form on one or more sidewalls of an STTM element during its formation. Devices and systems including such STTM elements are also described.

公开(公告)号：US10340443B2

公开(公告)日：2019-07-02

申请号：US15735613

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Brian S. Doyle ,  Kaan Oguz ,  Kevin P. O'Brien ,  David L. Kencke ,  Elijah V. Karpov ,  Charles C. Kuo ,  Mark L. Doczy ,  Satyarth Suri ,  Robert S. Chau ,  Niloy Mukherjee ,  Prashant Majhi

IPC: H01L43/02 ,  H01L43/08 ,  H01L45/00 ,  H01L27/22 ,  H01L43/10

Abstract: An embodiment includes an apparatus comprising: first and second electrodes on a substrate; a perpendicular magnetic tunnel junction (pMTJ), between the first and second electrodes, comprising a dielectric layer between a fixed layer and a free layer; and an additional dielectric layer directly contacting first and second metal layers; wherein (a) the first metal layer includes an active metal and the second metal includes an inert metal, and (b) the second metal layer directly contacts the free layer. Other embodiments are described herein.

公开(公告)号：US09882121B2

公开(公告)日：2018-01-30

申请号：US15117605

申请日：2014-03-28

Applicant: INTEL CORPORATION

Inventor： Charles C. Kuo ,  Kaan Oguz ,  Brian S. Doyle ,  Mark L. Doczy ,  David L. Kencke ,  Satyarth Suri ,  Robert S. Chau

IPC: H01L29/82 ,  H01L43/08 ,  H01L43/02 ,  G11C11/16 ,  H01L43/12

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L43/02 ,  H01L43/12

Abstract: Techniques are disclosed for fabricating a self-aligned spin-transfer torque memory (STTM) device with a dot-contacted free magnetic layer. In some embodiments, the disclosed STTM device includes a first dielectric spacer covering sidewalls of an electrically conductive hardmask layer that is patterned to provide an electronic contact for the STTM's free magnetic layer. The hardmask contact can be narrower than the free magnetic layer. The first dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer. In some embodiments, the STTM further includes an optional second dielectric spacer covering sidewalls of its free magnetic layer. The second dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer and may serve, at least in part, to protect the sidewalls of the free magnetic layer from redepositing of etch byproducts during such patterning, thereby preventing electrical shorting between the fixed magnetic layer and the free magnetic layer.

公开(公告)号：US09871117B2

公开(公告)日：2018-01-16

申请号：US15062007

申请日：2016-03-04

Applicant: Intel Corporation

Inventor： Brian S. Doyle ,  Uday Shah ,  Roza Kotlyar ,  Charles C. Kuo

IPC: H01L31/072 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/165 ,  H01L29/205 ,  H01L29/739 ,  H01L29/749 ,  H01L21/02 ,  H01L21/306 ,  H01L29/49 ,  H01L29/161 ,  H01L29/201 ,  H01L29/08

CPC classification number: H01L29/66666 ,  H01L21/02532 ,  H01L21/30604 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/201 ,  H01L29/205 ,  H01L29/4983 ,  H01L29/66356 ,  H01L29/66363 ,  H01L29/7391 ,  H01L29/749 ,  H01L29/7827 ,  H01L29/7848

Abstract: Vertical transistor devices are described. For example, in one embodiment, a vertical transistor device includes an epitaxial source semiconductor region disposed on a substrate, an epitaxial channel semiconductor region disposed on the source semiconductor region, an epitaxial drain semiconductor region disposed on the channel semiconductor region, and a gate electrode region surrounding sidewalls of the semiconductor channel region. A composition of at least one of the semiconductor regions varies along a longitudinal axis that is perpendicular with respect to a surface of the substrate.

公开(公告)号：US09754996B2

公开(公告)日：2017-09-05

申请号：US14312125

申请日：2014-06-23

Applicant: INTEL CORPORATION

Inventor： Brian S. Doyle ,  David L. Kencke ,  Charles C. Kuo ,  Dmitri E. Nikonov ,  Robert S. Chau

IPC: H01L29/82 ,  H01L27/22 ,  H01L43/08 ,  G11C11/16 ,  H01L43/02

CPC classification number: H01L27/228 ,  G11C11/161 ,  G11C11/1659 ,  H01L43/02 ,  H01L43/08

Abstract: The present disclosure relates to the fabrication of spin transfer torque memory elements for non-volatile microelectronic memory devices. The spin transfer torque memory element may include a magnetic tunneling junction connected with specifically sized and/or shaped fixed magnetic layer that can be positioned in a specific location adjacent a free magnetic layer. The shaped fixed magnetic layer may concentrate current in the free magnetic layer, which may result in a reduction in the critical current needed to switch a bit cell in the spin transfer torque memory element.