公开(公告)号：US20240105822A1

公开(公告)日：2024-03-28

申请号：US17953648

申请日：2022-09-27

Applicant: Intel Corporation

Inventor： Kevin P. O'Brien ,  Brandon Holybee ,  Carly Rogan ,  Dmitri Evgenievich Nikonov ,  Punyashloka Debashis ,  Rachel A. Steinhardt ,  Tristan A. Tronic ,  Ian Alexander Young ,  Marko Radosavljevic ,  John J. Plombon

IPC: H01L29/775 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/775 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66969

Abstract: A transistor device may include a first perovskite gate material, a first perovskite ferroelectric material on the first gate material, a first perovskite semiconductor material on the first ferroelectric material, a second perovskite ferroelectric material on the first semiconductor material, a second perovskite gate material on the second ferroelectric material, a third perovskite ferroelectric material on the second gate material, a second perovskite semiconductor material on the third ferroelectric material, a fourth perovskite ferroelectric material on the second semiconductor material, a third perovskite gate material on the fourth ferroelectric material, a first source/drain metal adjacent a first side of each of the first semiconductor material and the second semiconductor material, a second source/drain metal adjacent a second side opposite the first side of each of the first semiconductor material and the second semiconductor material, and dielectric materials between the source/drain metals and the gate materials.

公开(公告)号：US20230420364A1

公开(公告)日：2023-12-28

申请号：US17849207

申请日：2022-06-24

Applicant: Intel Corporation

Inventor： Kevin P. O'Brien ,  Tristan A. Tronic ,  Ande Kitamura ,  Ashish Verma Penumatcha ,  Carl Hugo Naylor ,  Chelsey Dorow ,  Kirby Maxey ,  Scott B. Clendenning ,  Sudarat Lee ,  Uygar E. Avci

IPC: H01L23/528 ,  H01L23/522 ,  H01L29/423 ,  H01L29/18 ,  H01L27/092 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L29/42392 ,  H01L29/18 ,  H01L27/0924 ,  H01L29/78696 ,  H01L29/66742

Abstract: A microelectronic device, a semiconductor package including the device, an IC device assembly including the package, and a method of making the device. The device includes a substrate; a first structure on the substrate, the first structure corresponding to a front end of line (FEOL) stack of the device and including a plurality of first transistors therein; and a second structure on the substrate, the second structure corresponding to a back end of line (BEOL) stack of the device, and including a plurality of second transistors therein, the plurality of second transistors including a transition metal dichalcogenide (TMD) material. The second transistors are part of a voltage regulation architecture to regulate voltage supply to the die.

公开(公告)号：US11640995B2

公开(公告)日：2023-05-02

申请号：US16616373

申请日：2017-06-20

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Brian S. Doyle ,  Kevin P. O'Brien ,  Abhishek A. Sharma ,  Elijah V. Karpov ,  Kaan Oguz

IPC: H01L29/78 ,  H01L27/24 ,  H01L29/06 ,  H01L29/51 ,  H01L21/28 ,  H01L27/22 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

Abstract: Ferroelectric field effect transistors (FeFETs) having band-engineered interface layers are described. In an example, an integrated circuit structure includes a semiconductor channel layer above a substrate. A metal oxide material is on the semiconductor channel layer, the metal oxide material having no net dipole. A ferroelectric oxide material is on the metal oxide material. A gate electrode is on the ferroelectric oxide material, the gate electrode having a first side and a second side opposite the first side. A first source/drain region is at the first side of the gate electrode, and a second source/drain region is at the second side of the gate electrode.

公开(公告)号：US11295884B2

公开(公告)日：2022-04-05

申请号：US16329309

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Kaan Oguz ,  Kevin P. O'Brien ,  Brian S. Doyle ,  Charles C. Kuo ,  Mark L. Doczy

IPC: H01F10/32 ,  H01L43/02 ,  G11C11/16 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: A perpendicular spin transfer torque memory (pSTTM) device incorporates a magnetic tunnel junction (MTJ) device having a free magnetic stack that includes a plurality of magnetic layers interleaved with a plurality of non-magnetic insert layers. The layers are arranged such that the topmost and bottommost layers are magnetic layers. The stacked design decreases the damping of the MTJ free magnetic stack, beneficially reducing the write current required to write to the pSTTM device. The stacked design further increases the interface anisotropy, thereby beneficially improving the stability of the pSTTM device. The non-magnetic interface layer may include tantalum, molybdenum, tungsten, hafnium, or iridium, or a binary alloy containing at least two of tantalum, molybdenum, tungsten hafnium, or iridium.

公开(公告)号：US11031545B2

公开(公告)日：2021-06-08

申请号：US16327603

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Kaan Oguz ,  Kevin P. O'Brien ,  Brian S. Doyle ,  Mark L. Doczy ,  Charles C. Kuo ,  Daniel G. Ouellette ,  Christopher J. Wiegand ,  Md Tofizur Rahman ,  Brian Maertz

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: Systems, apparatus, and methods for magnetoresitive memory are described. An apparatus for magnetoresitive memory includes a fixed layer, a free layer, and a tunneling barrier between the fixed layer and the free layer. The free layer is a new alloy consisting of a composition of Cobalt (Co), Iron (Fe), and Boron (B) intermixed with a non-magnetic metal according to a ratio. A thin insert layer of CoFeB may optionally be added between the alloy and the tunneling barrier.

公开(公告)号：US10770651B2

公开(公告)日：2020-09-08

申请号：US16463326

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： MD Tofizur Rahman ,  Christopher J. Wiegand ,  Kaan Oguz ,  Daniel G. Ouellette ,  Brian Maertz ,  Kevin P. O'Brien ,  Mark L. Doczy ,  Brian S. Doyle ,  Oleg Golonzka ,  Tahir Ghani

IPC: H01L27/22 ,  H01L43/02 ,  H01F10/32 ,  H01L43/10 ,  H01L43/12 ,  H01L43/00

Abstract: A material layer stack for a pSTTM device includes a fixed magnetic layer, a tunnel barrier disposed above the fixed magnetic layer and a free layer disposed on the tunnel barrier. The free layer further includes a stack of bilayers where an uppermost bilayer is capped by a magnetic layer including iron and where each of the bilayers in the free layer includes a non-magnetic layer such as Tungsten, Molybdenum disposed on the magnetic layer. In an embodiment, the non-magnetic layers have a combined thickness that is less than 15% of a combined thickness of the magnetic layers in the stack of bilayers. A stack of bilayers including non-magnetic layers in the free layer can reduce the saturation magnetization of the material layer stack for the pSTTM device and subsequently increase the perpendicular magnetic anisotropy.

公开(公告)号：US10411068B2

公开(公告)日：2019-09-10

申请号：US15767127

申请日：2015-11-23

Applicant: Intel Corporation

Inventor： Christopher J. Wiegand ,  Oleg Golonzka ,  Kaan Oguz ,  Kevin P. O'Brien ,  Tofizur Rahman ,  Brian S. Doyle ,  Tahir Ghani ,  Mark L. Doczy

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08

Abstract: Disclosed herein are electrical contacts for magnetoresistive random access memory (MRAM) devices and related memory structures, devices, and methods. For example, and electrical contact for an MRAM device may include: a tantalum region; a barrier region formed of a first material; and a passivation region formed of a second material and disposed between the tantalum region and the barrier region, wherein the second material includes tantalum nitride and is different from the first material.

公开(公告)号：US10403811B2

公开(公告)日：2019-09-03

申请号：US15503680

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Kevin P. O'Brien ,  Kaan Oguz ,  Brian S. Doyle ,  Mark L. Doczy ,  Charles C. Kuo ,  Robert S. Chau

IPC: G11C11/16 ,  H01L43/10 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01F10/32

Abstract: A material layer stack for a magnetic tunneling junction, the material layer stack including a fixed magnetic layer; a dielectric layer; a free magnetic layer; and an amorphous electrically-conductive seed layer, wherein the fixed magnetic layer is disposed between the dielectric layer and the seed layer. A non-volatile memory device including a material stack including an amorphous electrically-conductive seed layer; and a fixed magnetic layer juxtaposed and in contact with the seed layer. A method including forming an amorphous seed layer on a first electrode of a memory device; forming a material layer stack on the amorphous seed layer, the material stack including a dielectric layer disposed between a fixed magnetic layer and a free magnetic layer, wherein the fixed magnetic layer.

公开(公告)号：US10388858B2

公开(公告)日：2019-08-20

申请号：US15503357

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Kevin P. O'Brien ,  Brian S. Doyle ,  Kaan Oguz ,  Robert S. Chau ,  Satyarth Suri

IPC: H01L43/12 ,  G11C11/16 ,  H01L43/08 ,  H01L43/10

Abstract: A method including forming a device stack including a dielectric layer between a fixed magnetic layer and a free magnetic layer on a fully-crystalline sacrificial film or substrate including a crystal lattice similar to the crystal lattice of the dielectric material; and transferring the device stack from the sacrificial film to a device substrate. An apparatus including a device stack including a dielectric layer between a fixed magnetic layer and a free magnetic layer on a device substrate wherein the fixed magnetic layer and the free magnetic layer each have a crystalline lattice conforming to a crystalline lattice of the sacrificial film or substrate on which they were formed prior to transfer to the device substrate.

公开(公告)号：US10365894B2

公开(公告)日：2019-07-30

申请号：US15575334

申请日：2015-06-17

Applicant: Intel Corporation

Inventor： Charles C. Kuo ,  Justin S. Brockman ,  Juan G. Alzate Vinasco ,  Kaan Oguz ,  Kevin P. O'Brien ,  Brian S. Doyle ,  Mark L. Doczy ,  Satyarth Suri ,  Robert S. Chau ,  Prashant Majhi ,  Ravi Pillarisetty ,  Elijah V. Karpov

IPC: G06F7/58 ,  H01L43/02 ,  H01L43/08

Abstract: Described is an apparatus which comprises: a magnetic tunneling junction (MTJ) device with out-of-plane magnetizations for its free and fixed magnetic layers, and configured to have a magnetization offset away from a center and closer to a switching threshold of the MTJ device; and logic for generating random numbers according to a resistive state of the MTJ device.