公开(公告)号：US20200273751A1

公开(公告)日：2020-08-27

申请号：US16283673

申请日：2019-02-22

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Marko Radosavljevic ,  Han Wui Then ,  Paul B. Fischer

IPC: H01L21/8258 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L27/092 ,  H01L29/16 ,  H01L25/065 ,  H01L29/66 ,  H01L29/08 ,  H01L27/12 ,  H01L29/778

Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistors integrated on the same support structure as non-III-N transistors (e.g., Si-based transistors), using semiconductor layer transfer. In one aspect, a non-III-N transistor may be integrated with an III-N transistor by, first, depositing a semiconductor material layer, a portion of which will later serve as a channel material of the non-III-N transistor, on a support structure different from that on which the III-N semiconductor material for the III-N transistor is provided, and then performing layer transfer of said semiconductor material layer to the support structure with the III-N material, e.g., by oxide-to-oxide bonding, advantageously enabling implementation of both types of transistors on a single support structure. Such integration may reduce costs and improve performance by enabling integrated digital logic solutions for III-N transistors and by reducing losses incurred when power is routed off chip in a multi-chip package.

公开(公告)号：US20200227470A1

公开(公告)日：2020-07-16

申请号：US16249577

申请日：2019-01-16

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Paul B. Fischer ,  Zdravko Boos ,  Marko Radosavljevic ,  Sansaptak Dasgupta

IPC: H01L27/20 ,  H01L23/66 ,  H01L29/20 ,  H01P1/205

Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistors integrated on the same substrate or die as resonators of RF filters. An example IC structure includes a support structure (e.g., a substrate), a resonator, provided over a first portion of the support structure, and an III-N transistor, provided over a second portion of the support structure. The IC structure includes a piezoelectric material so that first and second electrodes of the resonator enclose a first portion of the piezoelectric material, while a second portion of the piezoelectric material is enclosed between the channel material of the III-N transistor and the support structure. In this manner, one or more resonators of an RF filter may be monolithically integrated with one or more III-N transistors. Such integration may reduce costs and improve performance by reducing RF losses incurred when power is routed off chip.

公开(公告)号：US20200227407A1

公开(公告)日：2020-07-16

申请号：US16249256

申请日：2019-01-16

Applicant: Intel Corporation

Inventor： Marko Radosavljevic ,  Han Wui Then ,  Sansaptak Dasgupta ,  Paul B. Fischer ,  Nidhi Nidhi ,  Rahul Ramaswamy ,  Johann Christian Rode ,  Walid M. Hafez

IPC: H01L27/07 ,  H01L49/02 ,  H01L29/20 ,  H01L29/778 ,  H01L29/66 ,  H01L29/423

Abstract: Disclosed herein are IC structures, packages, and devices that include polysilicon resistors, monolithically integrated on the same substrate/die/chip as III-N transistors. An example IC structure includes an III-N semiconductor material provided over a support structure, a III-N transistor provided over a first portion of the III-N material, and a polysilicon resistor provided over a second portion of the III-N material. Because the III-N transistor and the polysilicon resistor are both provided over a single support structure, they may be referred to as “integrated” transistors. Because the III-N transistor and the polysilicon resistor are provided over different portions of the III-N semiconductor material, and, therefore, over different portion of the support structure, their integration may be referred to as “side-by-side” integration.

公开(公告)号：US20200220004A1

公开(公告)日：2020-07-09

申请号：US16642866

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Marko Radosavljevic ,  Han Wui Then ,  Sansaptak Dasgupta

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/08

Abstract: A device including a III-N material is described. In an example, a device includes a first layer including a first group III-nitride (III-N) material and a polarization charge inducing layer, including a second III-N material, above the first layer. The device further includes a gate electrode above the polarization charge inducing layer and a source structure and a drain structure on opposite sides of the gate electrode. The source structure and the drain structure both include a first portion adjacent to the first layer and a second portion above the first portion, the first portion includes a third III-N material with an impurity dopant, and the second portion includes a fourth III-N material, where the fourth III-N material includes the impurity dopant and further includes indium, where the indium content increases with distance from the first portion.

公开(公告)号：US10693008B2

公开(公告)日：2020-06-23

申请号：US14914906

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Niloy Mukherjee ,  Marko Radosavljevic ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Niti Goel ,  Van H. Le ,  Gilbert Dewey ,  Benjamin Chu-Kung

IPC: H01L31/0256 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L29/423 ,  H01L29/786

Abstract: An apparatus including a semiconductor body including a channel region and junction regions disposed on opposite sides of the channel region, the semiconductor body including a first material including a first band gap; and a plurality of nanowires including a second material including a second band gap different than the first band gap, the plurality of nanowires disposed in separate planes extending through the first material so that the first material surrounds each of the plurality of nanowires; and a gate stack disposed on the channel region. A method including forming a plurality of nanowires in separate planes above a substrate, each of the plurality of nanowires including a material including a first band gap; individually forming a cladding material around each of the plurality of nanowires, the cladding material including a second band gap; coalescing the cladding material; and disposing a gate stack on the cladding material.

公开(公告)号：US10665707B2

公开(公告)日：2020-05-26

申请号：US15771752

申请日：2015-12-02

Applicant: INTEL CORPORATION

Inventor： Han Wui Then ,  Sansaptak Dasgupta ,  Marko Radosavljevic

IPC: H01L29/778 ,  H01L29/267 ,  H01L29/20 ,  H01L29/24 ,  H01L21/8258 ,  H01L27/092

Abstract: Techniques are disclosed for co-integrating transition metal dichalcogenide (TMDC)-based p-channel transistor devices and III-N semiconductor-based n-channel transistor devices. In accordance with some embodiments, a p-channel transistor device configured as described herein may include a layer of TMDC material such as, for example, tungsten diselenide, tungsten disulfide, molybdenum diselenide, or molybdenum disulfide, and an n-channel transistor device configured as described herein may include a layer of III-V material such as, for example, gallium nitride, aluminum nitride, aluminum gallium nitride, and indium aluminum nitride. Transistor structures provided as described herein may be utilized, for instance, in power delivery applications where III-N semiconductor-based n-channel power transistor devices can benefit from being integrated with low-leakage, high-performance p-channel devices providing logic and control circuitry. In some cases, a TMDC-based transistor provided as described herein may exhibit p-channel mobility in excess of bulk Si and thus may exhibit faster performance than traditional Si-based p-channel transistors.

公开(公告)号：US10535777B2

公开(公告)日：2020-01-14

申请号：US15940424

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： Marko Radosavljevic ,  Han Wui Then ,  Sansaptak Dasgupta

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/06 ,  H01L29/20 ,  H01L29/04 ,  H01L29/423 ,  H01L21/306 ,  H01L21/02

Abstract: Nanoribbon Field Effect Transistors (FETs) offer significant performance increases and energy consumption decreases relative to traditional metal oxide semiconductor (MOS) transistors. Various embodiments are directed to nanoribbon FETs having III-N channel materials and methods of forming the same. An integrated circuit (IC) structure can include a first layer on a substrate. The first layer can include a group III semiconductor material and nitrogen. The IC structure can include recessed source and drain regions formed on the first layer using planar epitaxy. The IC structure can include a second layer between the recessed source and drain. A gate wraps around at least part of the second layer.

公开(公告)号：US10475888B2

公开(公告)日：2019-11-12

申请号：US15492785

申请日：2017-04-20

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Han Wui Then ,  Seung Hoon Sung ,  Sanaz K. Gardner ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Robert S. Chau

IPC: H01L29/20 ,  H01L29/04 ,  H01L29/06 ,  H01L29/66 ,  H01L21/308 ,  H01L21/02

Abstract: An insulating layer is conformally deposited on a plurality of mesa structures in a trench on a substrate. The insulating layer fills a space outside the mesa structures. A nucleation layer is deposited on the mesa structures. A III-V material layer is deposited on the nucleation layer. The III-V material layer is laterally grown over the insulating layer.

公开(公告)号：US20190305135A1

公开(公告)日：2019-10-03

申请号：US15940424

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： Marko Radosavljevic ,  Han Wui Then ,  Sansaptak Dasgupta

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/20 ,  H01L29/04 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306

Abstract: Nanoribbon Field Effect Transistors (FETs) offer significant performance increases and energy consumption decreases relative to traditional metal oxide semiconductor (MOS) transistors. Various embodiments are directed to nanoribbon FETs having III-N channel materials and methods of forming the same. An integrated circuit (IC) structure can include a first layer on a substrate. The first layer can include a group III semiconductor material and nitrogen. The IC structure can include recessed source and drain regions formed on the first layer using planar epitaxy. The IC structure can include a second layer between the recessed source and drain. A gate wraps around at least part of the second layer.

公开(公告)号：US20190287858A1

公开(公告)日：2019-09-19

申请号：US16433277

申请日：2019-06-06

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Han Wui Then ,  Marko Radosavljevic ,  Sanaz Gardner ,  Seung Hoon Sung

IPC: H01L21/8258 ,  H01L21/02 ,  H01L21/8252 ,  H01L27/085 ,  H01L27/06 ,  H01L29/08 ,  H01L27/092 ,  H01L29/778 ,  H01L29/66

Abstract: Techniques are disclosed for fabricating co-planar p-channel and n-channel gallium nitride (GaN)-based transistors on silicon (Si). In accordance with some embodiments, a Si substrate may be patterned with recessed trenches located under corresponding openings formed in a dielectric layer over the substrate. Within each recessed trench, a stack including a buffer layer, a GaN or indium gallium nitride (InGaN) layer, and a polarization layer may be selectively formed, in accordance with some embodiments. The p-channel stack further may include another GaN or InGaN layer over its polarization layer, with source/drain (S/D) portions adjacent the m-plane or a-plane sidewalls of that GaN or InGaN layer. The n-channel may include S/D portions over its GaN or InGaN layer, within its polarization layer, in accordance with some embodiments. Gate stack placement can be customized to provide any desired combination of enhancement and depletion modes for the resultant neighboring p-channel and n-channel transistor devices.