公开(公告)号：US10062671B2

公开(公告)日：2018-08-28

申请号：US15134984

申请日：2016-04-21

Applicant: Infineon Technologies AG

Inventor： Martin Gruber ,  Angela Kessler ,  Thorsten Scharf

IPC: H05K1/18 ,  H01L25/07 ,  H01L23/367 ,  H01L23/498 ,  H01L25/11 ,  H01L25/16

CPC classification number: H01L25/072 ,  H01L23/3672 ,  H01L23/49811 ,  H01L25/115 ,  H01L25/16

Abstract: A semiconductor module includes a circuit board and a power semiconductor chip embedded in the circuit board. The power semiconductor chip has a first load electrode. The semiconductor module further includes a power terminal connector electrically connected to the first load electrode. The embedded power semiconductor chip is positioned laterally within a footprint zone of the power terminal connector.

公开(公告)号：US20170229399A1

公开(公告)日：2017-08-10

申请号：US15426158

申请日：2017-02-07

Applicant: Infineon Technologies AG

Inventor： Martin Gruber ,  Steffen Jordan

IPC: H01L23/538 ,  H01L23/31 ,  H01L21/683 ,  H01L21/288 ,  H01L23/58 ,  H01L25/065 ,  H01L21/56 ,  H01L21/768

CPC classification number: H01L23/5389 ,  C23C18/1653 ,  C25D7/00 ,  H01L21/2885 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76873 ,  H01L21/76877 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/585 ,  H01L24/00 ,  H01L25/0655 ,  H01L2221/68359

Abstract: The method comprises providing a plurality of electronic devices, embedding the electronic devices in an encapsulation layer, forming vias into the encapsulation layer, the vias extending from a main face of the encapsulation layer to the electronic devices, and depositing a metallic layer onto the encapsulation layer including the vias by galvanic plating, the method further comprising providing a current distribution layer for effecting a distributed growth of the metallic material during the galvanic plating.

公开(公告)号：US20230051100A1

公开(公告)日：2023-02-16

申请号：US17980004

申请日：2022-11-03

Applicant: Infineon Technologies AG

Inventor： Bun Kian Tay ,  Mei Yih Goh ,  Martin Gruber ,  Josef Hoeglauer ,  Michael Juerss ,  Josef Maerz ,  Thorsten Meyer ,  Thorsten Scharf ,  Chee Voon Tan

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L23/495 ,  H01L21/48

Abstract: A molded semiconductor package includes a lead frame having one or more first leads monolithically formed with a die pad and extending outward from the pad in a first direction. A semiconductor die is attached to the die pad at a first side of the die. A metal clip of a clip frame is attached to a power terminal at a second side of the die. One or more second leads monolithically formed with the metal clip extend outward from the clip in a second direction different than the first direction. A mold compound embeds the die. The first lead(s) and the second lead(s) are exposed at different sides of the mold compound and do not vertically overlap with one another. Within the mold compound, the clip transitions from a first level above the power terminal to a second level in a same plane as the leads.

公开(公告)号：US20220285283A1

公开(公告)日：2022-09-08

申请号：US17752224

申请日：2022-05-24

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Ravi Keshav Joshi ,  Ralf Siemieniec ,  Thomas Basler ,  Martin Gruber ,  Jochen Hilsenbeck ,  Dethard Peters ,  Roland Rupp ,  Wolfgang Scholz

IPC: H01L23/532 ,  H01L29/16 ,  H01L21/768 ,  H01L23/00 ,  H01L29/45

Abstract: A power semiconductor device includes a semiconductor substrate having a wide bandgap semiconductor material and a first surface, an insulation layer above the first surface of the semiconductor substrate, the insulation layer including at least one opening extending through the insulation layer in a vertical direction, a front metallization above the insulation layer with the insulation layer being interposed between the front metallization and the first surface of the semiconductor substrate, and a metal connection arranged in the opening of the insulation layer and electrically conductively connecting the front metallization with the semiconductor substrate; wherein the front metallization includes at least one layer that is a metal or a metal alloy having a higher melting temperature than an intrinsic temperature of the wide bandgap semiconductor material of the semiconductor substrate.

公开(公告)号：US20200006187A1

公开(公告)日：2020-01-02

申请号：US16452777

申请日：2019-06-26

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Irmgard Escher-Poeppel ,  Martin Gruber ,  Michael Juerss ,  Thorsten Scharf

IPC: H01L23/367 ,  H01L23/495 ,  H01L23/532 ,  H01L23/373 ,  H01L23/31

Abstract: A heat dissipation device includes a first part having a first material and a surface portion, and a second part on the surface portion. The second part has a second material and a porosity.

公开(公告)号：US20190304858A1

公开(公告)日：2019-10-03

申请号：US16365837

申请日：2019-03-27

Applicant: Infineon Technologies AG

Inventor： Thorsten Scharf ,  Ralf Otremba ,  Thomas Bemmerl ,  Irmgard Escher-Poeppel ,  Martin Gruber ,  Michael Juerss ,  Thorsten Meyer ,  Xaver Schloegel

IPC: H01L23/053 ,  H01L23/40 ,  H01L23/00 ,  H01L23/08

Abstract: A semiconductor package system comprises a semiconductor package and a cap. The semiconductor package comprises a die pad, a chip mounted or arranged to a first main face of the die pad and an encapsulation body encapsulating the chip and the die pad. The cap covers at least partly an exposed second main face of the die pad. The cap comprises a cap body of an electrically insulating and thermally conductive material and a fastening system fastening the cap to the semiconductor package. The fastening system extends from the cap body towards the encapsulation body or along a side surface of the semiconductor package.

公开(公告)号：US20190157190A1

公开(公告)日：2019-05-23

申请号：US15816090

申请日：2017-11-17

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Martin Gruber

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

Abstract: A semiconductor device package includes a lead frame, a first power semiconductor device mounted on a first part of the lead frame and a second power semiconductor device mounted on a second part of the lead frame. The first power semiconductor device is encapsulated by a first mold compound. The second power semiconductor device is encapsulated by a second mold compound. The first mold compound and the second mold compound are substantially separate from each other. The lead frame includes an intermediate part arranged between the first part and the second part. The intermediate part is not covered by the first mold compound or by the second mold compound.

公开(公告)号：US10229885B2

公开(公告)日：2019-03-12

申请号：US15426158

申请日：2017-02-07

Applicant: Infineon Technologies AG

Inventor： Martin Gruber ,  Steffen Jordan

IPC: H01L23/538 ,  H01L23/58 ,  C23C18/16 ,  C25D7/00 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00 ,  H01L25/065 ,  H01L21/288 ,  H01L23/31

Abstract: The method comprises providing a plurality of electronic devices, embedding the electronic devices in an encapsulation layer, forming vias into the encapsulation layer, the vias extending from a main face of the encapsulation layer to the electronic devices, and depositing a metallic layer onto the encapsulation layer including the vias by galvanic plating, the method further comprising providing a current distribution layer for effecting a distributed growth of the metallic material during the galvanic plating.

公开(公告)号：US20160316567A1

公开(公告)日：2016-10-27

申请号：US15134984

申请日：2016-04-21

Applicant: Infineon Technologies AG

Inventor： Martin Gruber ,  Angela Kessler ,  Thorsten Scharf

IPC: H05K1/18 ,  H05K3/32 ,  H05K1/11 ,  H05K1/02 ,  H01L25/07

CPC classification number: H01L25/072 ,  H01L23/3672 ,  H01L23/49811 ,  H01L25/115 ,  H01L25/16

Abstract: A semiconductor module includes a circuit board and a power semiconductor chip embedded in the circuit board. The power semiconductor chip has a first load electrode. The semiconductor module further includes a power terminal connector electrically connected to the first load electrode. The embedded power semiconductor chip is positioned laterally within a footprint zone of the power terminal connector.

Abstract translation: 半导体模块包括电路板和埋入电路板中的功率半导体芯片。 功率半导体芯片具有第一负载电极。 半导体模块还包括电连接到第一负载电极的电源端子连接器。 嵌入式功率半导体芯片横向定位在电源端子连接器的覆盖区域内。

公开(公告)号：US20250054843A1

公开(公告)日：2025-02-13

申请号：US18931698

申请日：2024-10-30

Applicant: Infineon Technologies AG

Inventor： Frank Singer ,  Marcus Böhm ,  Andreas Grassmann ,  Martin Gruber ,  Uwe Schindler

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

Abstract: A package includes a carrier, an electronic component on the carrier, an encapsulant encapsulating at least part of the carrier and the electronic component, and at least one lead extending beyond the encapsulant and having a punched surface, wherein at least part of at least one side flank of the encapsulant has a sawn texture.