公开(公告)号：US12027490B2

公开(公告)日：2024-07-02

申请号：US17390101

申请日：2021-07-30

Applicant: Infineon Technologies AG

Inventor： Richard Knipper ,  Alexander Heinrich ,  Thorsten Scharf ,  Stefan Schwab

IPC: H01L23/00

CPC classification number: H01L24/85 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45033 ,  H01L2224/48472 ,  H01L2224/85205 ,  H01L2224/85214 ,  H01L2224/85825

Abstract: A method for fabricating a semiconductor device includes providing a semiconductor die, arranging an electrical connector over the semiconductor die, the electrical connector including a conductive core, an absorbing feature arranged on a first side of the conductive core, and a solder layer arranged on a second side of the conductive core, opposite the first side and facing the semiconductor die, and soldering the electrical connector onto the semiconductor die by heating the solder layer with a laser, wherein the laser irradiates the absorbing feature and absorbed energy is transferred from the absorbing feature through the conductive core to the solder layer.

公开(公告)号：US11862600B2

公开(公告)日：2024-01-02

申请号：US17491647

申请日：2021-10-01

Applicant: Infineon Technologies AG

Inventor： Thorsten Scharf ,  Alexander Heinrich ,  Steffen Jordan

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L24/80 ,  H01L21/565 ,  H01L23/4985 ,  H01L2224/80357 ,  H01L2224/83385 ,  H01L2924/1511 ,  H01L2924/15724 ,  H01L2924/15738

Abstract: A method of forming a chip package is provided. The method includes providing a malleable carrier with a layer of an electrically conductive material formed thereon, and positive fitting the malleable carrier to a chip to at least partially enclose the chip with the malleable carrier. The layer at least partially physically contacts the chip, such that the layer electrically contacts a chip contact of the chip. The layer forms a redistribution layer.

公开(公告)号：US20230361087A1

公开(公告)日：2023-11-09

申请号：US17736519

申请日：2022-05-04

Applicant: Infineon Technologies AG

Inventor： Ivan Nikitin ,  Thorsten Scharf ,  Marco Baessler ,  Andreas Grassmann ,  Waldemar Jakobi

IPC: H01L25/07 ,  H01L23/498 ,  H01L23/495

CPC classification number: H01L25/072 ,  H01L23/49811 ,  H01L23/49537 ,  H01L23/49575 ,  H01L23/49833 ,  H01L23/4952 ,  H01L23/3121

Abstract: A molded power semiconductor package includes: at least one first power electronics carrier having a metallization layer disposed on an electrically insulating substrate; a plurality of first power semiconductor dies attached to the metallization layer of the at least one first power electronics carrier; at least one second power electronics carrier having a metallization layer disposed on an electrically insulating substrate; a plurality of second power semiconductor dies attached to the metallization layer of the at least one second power electronics carrier; and a mold compound encasing the plurality of first power semiconductor dies and the plurality of second power semiconductor dies, and at least partly encasing the at least one first power electronics carrier and the at least one second power electronics carrier. The at least one first power electronics carrier and the at least one second power electronics carrier lie in a same plane.

公开(公告)号：US20230197577A1

公开(公告)日：2023-06-22

申请号：US18082238

申请日：2022-12-15

Applicant: Infineon Technologies AG

Inventor： Thorsten Scharf ,  Josef Höglauer ,  Angela Kessler ,  Claus Waechter

IPC: H01L23/495 ,  H01L23/31 ,  H01L25/16 ,  H01L25/00

CPC classification number: H01L23/49541 ,  H01L23/3107 ,  H01L23/49534 ,  H01L25/16 ,  H01L25/50

Abstract: A semiconductor device includes a premolded leadframe, including a main surface, at least one electrical contact extending out of the main surface, and an opposite main surface arranged opposite to the main surface. The semiconductor device further includes a semiconductor package arranged on the main surface and laterally displaced to the at least one electrical contact of the premolded leadframe. The semiconductor package includes a semiconductor chip and at least one electrical contact. Surfaces of the at least one electrical contact of the premolded leadframe and the at least one electrical contact of the semiconductor package facing away from the main surface are flush.

公开(公告)号：US11515244B2

公开(公告)日：2022-11-29

申请号：US16748049

申请日：2020-01-21

Applicant: Infineon Technologies AG

Inventor： Bun Kian Tay ,  Mei Yih Goh ,  Martin Gruber ,  Josef Hoeglauer ,  Michael Juerss ,  Josef Maerz ,  Thorsten Meyer ,  Thorsten Scharf ,  Chee Voon Tan

IPC: H01L23/495 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

Abstract: A molded semiconductor package includes a lead frame having one or more first leads monolithically formed with a die pad and extending outward from the pad in a first direction. A semiconductor die is attached to the die pad at a first side of the die. A metal clip of a clip frame is attached to a power terminal at a second side of the die. One or more second leads monolithically formed with the metal clip extend outward from the clip in a second direction different than the first direction. A mold compound embeds the die. The first lead(s) and the second lead(s) are exposed at different sides of the mold compound and do not vertically overlap with one another. Within the mold compound, the clip transitions from a first level above the power terminal to a second level in a same plane as the leads.

公开(公告)号：US11264356B2

公开(公告)日：2022-03-01

申请号：US16842417

申请日：2020-04-07

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Thomas Behrens ,  Andreas Grassmann ,  Martin Gruber ,  Thorsten Scharf

IPC: H01L21/78 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/495 ,  H01L23/31

Abstract: A method of manufacturing packages is disclosed. In one example, the method comprises providing an electrically conductive sheet being continuous at least in a mounting region, mounting first main surfaces of a plurality of electronic components on the continuous mounting region of the sheet and forming interconnect structures for electrically coupling second main surfaces of the electronic components with the sheet. The second main surfaces oppose the first main surfaces. After the forming, structuring the sheet.

公开(公告)号：US20210057234A1

公开(公告)日：2021-02-25

申请号：US16546913

申请日：2019-08-21

Applicant: Infineon Technologies AG

Inventor： Richard Knipper ,  Thorsten Scharf

IPC: H01L21/56 ,  H01L23/00 ,  H01L21/48 ,  H01L21/027 ,  H01L21/78 ,  H01L23/31

Abstract: A method includes: providing a semiconductor die having a first main surface, a second main surface opposite the first main surface, and an edge between the first main surface and the second main surface; applying a temporary spacer to a first part of the first main surface of the semiconductor die, the first part being positioned inward from a peripheral part of the first main surface; after applying the temporary spacer, embedding the semiconductor die at least partly in an embedding material, the embedding material covering the edge and the peripheral part of the first main surface of the semiconductor die and contacting a sidewall of the temporary spacer; and after the embedding, removing the temporary spacer from the first main surface of the semiconductor die to expose the first part of the first main surface of the semiconductor die. A semiconductor device produced by the method is also provided.

公开(公告)号：US10777491B2

公开(公告)日：2020-09-15

申请号：US16280181

申请日：2019-02-20

Applicant: Infineon Technologies AG

Inventor： Thorsten Scharf ,  Thorsten Meyer

IPC: H01L23/40 ,  H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L25/10

Abstract: A package comprising a carrier, at least one electronic chip mounted on one side of the carrier, an encapsulant at least partially encapsulating the at least one electronic chip and partially encapsulating the carrier, and at least one component attached to an opposing other side of the carrier via at least one contact opening.

公开(公告)号：US20200273790A1

公开(公告)日：2020-08-27

申请号：US16748049

申请日：2020-01-21

Applicant: Infineon Technologies AG

Inventor： Bun Kian Tay ,  Mei Yih Goh ,  Martin Gruber ,  Josef Hoeglauer ,  Michael Juerss ,  Josef Maerz ,  Thorsten Meyer ,  Thorsten Scharf ,  Chee Voon Tan

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/495 ,  H01L21/48 ,  H01L21/56

Abstract: A molded semiconductor package includes a lead frame having one or more first leads monolithically formed with a die pad and extending outward from the pad in a first direction. A semiconductor die is attached to the die pad at a first side of the die. A metal clip of a clip frame is attached to a power terminal at a second side of the die. One or more second leads monolithically formed with the metal clip extend outward from the clip in a second direction different than the first direction. A mold compound embeds the die. The first lead(s) and the second lead(s) are exposed at different sides of the mold compound and do not vertically overlap with one another. Within the mold compound, the clip transitions from a first level above the power terminal to a second level in a same plane as the leads.

公开(公告)号：US10056348B2

公开(公告)日：2018-08-21

申请号：US15632680

申请日：2017-06-26

Applicant: Infineon Technologies AG

Inventor： Petteri Palm ,  Thorsten Scharf ,  Ralf Wombacher

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/48 ,  H01L21/78 ,  H01L23/538

CPC classification number: H01L24/82 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/055 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/25 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/8285 ,  H01L2224/83005 ,  H01L2224/83132 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/82 ,  H01L2224/83

Abstract: Electronic module (100), which comprises a first substrate (102), a first dielectric layer (104) on the first substrate (102), at least one electronic chip (106), which is mounted with a first main surface (108) directly or indirectly on partial region of the first dielectric layer (104), a second substrate (110) over a second main surface (114) of the at least one electronic chip (106), and an electrical contacting (116) for the electric contact of the at least one electronic chip (106) through the first dielectric layer (104), wherein the first adhesion layer (104) on the first substrate (102) extends over an area, which exceeds the first main surface (108).