公开(公告)号：US20230095749A1

公开(公告)日：2023-03-30

申请号：US17947353

申请日：2022-09-19

Applicant: Infineon Technologies AG

Inventor： Alexander Heinrich ,  Alexander Roth ,  Catharina Wille

IPC: H01L23/00 ,  B23K35/02 ,  B23K35/26

Abstract: A solder material is provided. The solder material may include a first amount of particles having particle sizes forming a first size distribution, a second amount of particles having particle sizes forming a second size distribution, the particle sizes of the second size distribution being larger than the particle sizes of the first size distribution, and a solder base material in which the first amount of particles and the second amount of particles is distributed. The first amount of particles and the second amount of particles consist of or essentially consist of a metal of a first group of metals. The first group of metals includes copper, silver, gold, palladium, platinum, iron, cobalt, and aluminum. The solder base material includes a metal of a second group of metals. The second group of metals includes tin, indium, zinc, gallium, germanium, antimony, and bismuth.

公开(公告)号：US11424217B2

公开(公告)日：2022-08-23

申请号：US16943084

申请日：2020-07-30

Applicant: Infineon Technologies AG

Inventor： Alexander Heinrich ,  Ralf Otremba ,  Stefan Schwab

IPC: H01L23/00 ,  H01L29/45

Abstract: An arrangement is disclosed. In one example, the arrangement of a conductor and an aluminum layer soldered together comprises a substrate and the aluminum layer disposed over the substrate. The aluminum forms a first bond metal. An intermetallic compound layer is disposed over the aluminum layer. A solder layer is disposed over the intermetallic compound layer, wherein the solder comprises a low melting majority component. The conductor is disposed over the solder layer, wherein the conductor has a soldering surface which comprises a second bond metal. The intermetallic compound comprises aluminum and the second bond metal and is predominantly free of the low melting majority component.

公开(公告)号：US20220216173A1

公开(公告)日：2022-07-07

申请号：US17376372

申请日：2021-07-15

Applicant: Infineon Technologies AG

Inventor： Thomas Behrens ,  Alexander Heinrich ,  Evelyn Napetschnig ,  Bernhard Weidgans ,  Catharina Wille ,  Christina Yeong

IPC: H01L23/00 ,  B23K35/26 ,  C22C13/02

Abstract: A semiconductor device and method is disclosed. In one embodiment, the semiconductor device comprises a semiconductor die comprising a first surface and a second surface opposite to the first surface, a first metallization layer disposed on the first surface of the semiconductor die, a first solder layer disposed on the first metallization layer, wherein the first solder layer contains the compound Sn/Sb, and a first contact member comprising a Cu-based base body and a Ni-based layer disposed on a main surface of the Cu-based base body, wherein the first contact member is connected with the Ni-based layer to the first solder layer.

公开(公告)号：US20220108974A1

公开(公告)日：2022-04-07

申请号：US17491647

申请日：2021-10-01

Applicant: Infineon Technologies AG

Inventor： Thorsten Scharf ,  Alexander Heinrich ,  Steffen Jordan

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/498

Abstract: A method of forming a chip package is provided. The method includes providing a malleable carrier with a layer of an electrically conductive material formed thereon, and positive fitting the malleable carrier to a chip to at least partially enclose the chip with the malleable carrier. The layer at least partially physically contacts the chip, such that the layer electrically contacts a chip contact of the chip. The layer forms a redistribution layer.

公开(公告)号：US11069644B2

公开(公告)日：2021-07-20

申请号：US16556823

申请日：2019-08-30

Applicant: Infineon Technologies AG

Inventor： Thomas Behrens ,  Alexander Heinrich ,  Evelyn Napetschnig ,  Bernhard Weidgans ,  Catharina Wille ,  Christina Yeong

IPC: H01L23/00 ,  B23K35/26 ,  C22C13/02

Abstract: A semiconductor device and method is disclosed. In one embodiment, the semiconductor device comprises a semiconductor die comprising a first surface and a second surface opposite to the first surface, a first metallization layer disposed on the first surface of the semiconductor die, a first solder layer disposed on the first metallization layer, wherein the first solder layer contains the compound Sn/Sb, and a first contact member comprising a Cu-based base body and a Ni-based layer disposed on a main surface of the Cu-based base body, wherein the first contact member is connected with the Ni-based layer to the first solder layer.

公开(公告)号：US20200243480A1

公开(公告)日：2020-07-30

申请号：US16820057

申请日：2020-03-16

Applicant: Infineon Technologies AG

Inventor： Edmund Riedl ,  Wu Hu Li ,  Alexander Heinrich ,  Ralf Otremba ,  Werner Reiss

IPC: H01L23/00 ,  H01L23/498 ,  B23K35/26 ,  B23K1/00 ,  B23K35/28 ,  B23K1/20 ,  B23K101/38

Abstract: A method of making a semiconductor including soldering a conductor to an aluminum metallization is disclosed. In one example, the method includes substituting an aluminum oxide layer on the aluminum metallization by a substitute metal oxide layer or a substitute metal alloy oxide layer. Then, substitute metal oxides in the substitute metal oxide layer or the substitute metal alloy oxide layer are at least partly reduced. The conductor is soldered to the aluminum metallization using a solder material.

公开(公告)号：US20200035645A1

公开(公告)日：2020-01-30

申请号：US16523789

申请日：2019-07-26

Applicant: Infineon Technologies AG

Inventor： Alexander Heinrich ,  Frank Daeche

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/13

Abstract: A chip assembly includes a carrier and a metal grid array having an opening. The metal grid array is attached to the carrier by an attachment material. The metal grid array and the carrier define a cavity which is formed by the opening and the carrier. The chip assembly further includes an electronic chip mounted in the cavity.

公开(公告)号：US20180096966A1

公开(公告)日：2018-04-05

申请号：US15284580

申请日：2016-10-04

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Gerald Ofner ,  Peter Scherl ,  Stephan Bradl ,  Stefan Miethaner ,  Alexander Heinrich ,  Horst Theuss

IPC: H01L23/00 ,  H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

Abstract: A method of producing packaged semiconductor devices includes providing a first packaging substrate panel. A second packaging substrate panel is provided. The first and second packaging substrate panels are moved through an assembly line that includes a plurality of package assembly tools using a control mechanism. First type packaged semiconductor devices are formed on the first packaging substrate panel and second type packaged semiconductor devices are formed on the second packaging substrate panel. The second type packaged semiconductor device is different than the first type packaged semiconductor device. The control mechanism moves both of the first and packaging substrate panels through the assembly line in a non-linear manner.

公开(公告)号：US09673170B2

公开(公告)日：2017-06-06

申请号：US14451868

申请日：2014-08-05

Applicant: Infineon Technologies AG

Inventor： Rupert Fischer ,  Peter Strobel ,  Joachim Mahler ,  Konrad Roesl ,  Alexander Heinrich

IPC: H01L21/68 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H01L21/683 ,  H01L23/495 ,  H01L23/29 ,  H01L23/31

CPC classification number: H01L24/97 ,  H01L21/6835 ,  H01L23/295 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/49575 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68354 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2224/04026 ,  H01L2224/05611 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/06181 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/40227 ,  H01L2224/40247 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/8381 ,  H01L2224/8382 ,  H01L2224/83851 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2224/95001 ,  H01L2224/95091 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/84 ,  H01L2224/27 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2924/00

Abstract: Methods for connecting chips to a chip carrier are disclosed. In some embodiments the method for connecting a plurality of chips to a chip carrier includes placing first chips on a transfer carrier, placing second chips on the transfer carrier, placing the transfer carrier with the first and second chips on the chip carrier and forming connections between the first chips and the chip carrier and the second chips and the chip carrier.

公开(公告)号：US20170033066A1

公开(公告)日：2017-02-02

申请号：US15295631

申请日：2016-10-17

Applicant: Infineon Technologies AG

Inventor： Evelyn Napetschnig ,  Ulrike Fastner ,  Alexander Heinrich ,  Thomas Fischer

IPC: H01L23/00 ,  H01L21/304 ,  H01L21/268 ,  H01L23/31 ,  H01L21/78

CPC classification number: H01L24/05 ,  H01L21/268 ,  H01L21/304 ,  H01L21/3086 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3107 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/27 ,  H01L24/29 ,  H01L24/94 ,  H01L24/96 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02205 ,  H01L2224/03009 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05005 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05172 ,  H01L2224/05554 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/0566 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/10126 ,  H01L2224/11009 ,  H01L2224/11011 ,  H01L2224/11019 ,  H01L2224/1134 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11845 ,  H01L2224/13007 ,  H01L2224/13013 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13105 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/26125 ,  H01L2224/27009 ,  H01L2224/27019 ,  H01L2224/2746 ,  H01L2224/2747 ,  H01L2224/27845 ,  H01L2224/29007 ,  H01L2224/29013 ,  H01L2224/291 ,  H01L2224/29105 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29118 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/94 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/206 ,  H01L2924/2064 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01032 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/27

Abstract: In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a contact layer over a first major surface of a substrate. The substrate includes device regions separated by kerf regions. The contact layer is disposed in the kerf region and the device regions. A structured solder layer is formed over the device regions. The contact layer is exposed at the kerf region after forming the structured solder layer. The contact layer and the substrate in the kerf regions are diced.

Abstract translation: 根据本发明的实施例，形成半导体器件的方法包括在衬底的第一主表面上形成接触层。 衬底包括由切口区域分隔开的器件区域。 接触层设置在切口区域和器件区域中。 在器件区域上形成结构化的焊料层。 在形成结构化的焊料层之后，在切割区域处露出接触层。 切割区域中的接触层和基底。