公开(公告)号：US11211489B2

公开(公告)日：2021-12-28

申请号：US16650793

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Brian Doyle ,  Abhishek Sharma ,  Elijah Karpov ,  Ravi Pillarisetty ,  Prashant Majhi

IPC: H01L29/78 ,  H01L29/66

Abstract: Low resistance field-effect transistors and methods of manufacturing the same are disclosed herein. An example field-effect transistor disclosed herein includes a substrate and a stack above the substrate. The stack includes an insulator and a gate electrode. The example field-effect transistor includes a semiconductor material layer in a cavity in the stack. In the example field-effect transistor, a region of the semiconductor material layer proximate to the insulator is doped with a material of the insulator.

公开(公告)号：US10347830B2

公开(公告)日：2019-07-09

申请号：US16046189

申请日：2018-07-26

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Elijah Ilya Karpov ,  Brian Doyle ,  Dmitri E. Nikonov ,  Ian Young

IPC: H01L45/00 ,  G06F12/02 ,  G11C14/00 ,  G11C11/16 ,  G11C8/16 ,  G11C11/00 ,  G11C13/00 ,  H01L27/02 ,  H01L27/24

Abstract: Some embodiments include apparatuses and methods having a memory element included in a non-volatile memory cell, a transistor, an access line coupled to a gate to the transistor, a first conductive line, and a second conductive line. The memory element can include a conductive oxide material located over a substrate and between the first and second conductive lines. The memory element includes a portion coupled to a drain of the transistor and another portion coupled to the second conductive line. The first conductive line is coupled to a source of the transistor and can be located between the access line and the memory element. The access line has a length extending in a first direction and can be located between the substrate and the memory element. The first and second conductive lines have lengths extending in a second direction.

公开(公告)号：US09736936B2

公开(公告)日：2017-08-15

申请号：US15012557

申请日：2016-02-01

Applicant: Intel Corporation

Inventor： Christopher Jezewski ,  Ravi Pillarisetty ,  Brian Doyle

IPC: H01L21/44 ,  H05K1/03 ,  D03D1/00 ,  D03D11/02 ,  D03D15/00 ,  H05K3/00 ,  H05K1/02 ,  H05K3/10 ,  H05K3/32 ,  H05K1/18 ,  H05K3/28

CPC classification number: H05K1/038 ,  D03D1/0088 ,  D03D11/02 ,  D03D15/00 ,  H05K1/028 ,  H05K1/0393 ,  H05K1/189 ,  H05K3/0058 ,  H05K3/10 ,  H05K3/28 ,  H05K3/284 ,  H05K3/32 ,  H05K2201/0145 ,  H05K2201/015 ,  H05K2201/0154 ,  H05K2201/0158 ,  H05K2201/029

Abstract: A system comprises an article comprising one or more fabric layers, a plurality of electronic devices, each being incorporated into or onto one of the one or more fabric layers, and one or more communication links between two or more of the plurality of electronic devices. Each of the plurality of electronic devices can comprise a flexible substrate coupled to the fabric layer, one or more metallization layers deposited on the flexible substrate, and one or more electronic components electrically coupled to the one or more metallization layers.

公开(公告)号：US09253884B2

公开(公告)日：2016-02-02

申请号：US14136428

申请日：2013-12-20

Applicant: Intel Corporation

Inventor： Christopher Jezewski ,  Ravi Pillarisetty ,  Brian Doyle

IPC: H01L23/52 ,  H05K1/03 ,  D03D1/00 ,  D03D11/02 ,  D03D15/00 ,  H05K3/00 ,  H05K1/18 ,  H05K3/28

CPC classification number: H05K1/038 ,  D03D1/0088 ,  D03D11/02 ,  D03D15/00 ,  H05K1/028 ,  H05K1/0393 ,  H05K1/189 ,  H05K3/0058 ,  H05K3/10 ,  H05K3/28 ,  H05K3/284 ,  H05K3/32 ,  H05K2201/0145 ,  H05K2201/015 ,  H05K2201/0154 ,  H05K2201/0158 ,  H05K2201/029

Abstract: A system comprises an article comprising one or more fabric layers, a plurality of electronic devices, each being incorporated into or onto one of the one or more fabric layers, and one or more communication links between two or more of the plurality of electronic devices. Each of the plurality of electronic devices can comprise a flexible substrate coupled to the fabric layer, one or more metallization layers deposited on the flexible substrate, and one or more electronic components electrically coupled to the one or more metallization layers.

Abstract translation: 系统包括包括一个或多个织物层的制品，多个电子装置，每个电子装置并入到一个或多个织物层中的一个或多个织物层中的一个上，以及多个电子装置中的两个或更多个之间的一个或多个通信连接。 多个电子设备中的每一个可以包括耦合到织物层的柔性衬底，沉积在柔性衬底上的一个或多个金属化层以及电耦合到一个或多个金属化层的一个或多个电子部件。

公开(公告)号：US09224794B2

公开(公告)日：2015-12-29

申请号：US13868273

申请日：2013-04-23

Applicant: Intel Corporation

Inventor： Steven Keating ,  Nick Lindert ,  Nadia Rahhal-Orabi ,  Brian Doyle ,  Satyarth Suri ,  Swaminathan Sivakumar ,  Lana Jong ,  Lin Sha

IPC: H01L29/92 ,  H01L49/02 ,  H01G4/012 ,  H01G4/33 ,  H01L23/522 ,  H01L27/108

CPC classification number: H01L28/40 ,  H01G4/012 ,  H01G4/33 ,  H01L23/5223 ,  H01L27/10852 ,  H01L28/90 ,  H01L28/91 ,  H01L28/92 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of patterning a metal (141, 341, 841) on a vertical sidewall (132, 332, 832) of an excavated feature (130, 330, 830) includes placing a material (350) in the excavated feature such that a portion (435) of the metal is exposed in the excavated feature above the material, etching the exposed portion of the metal away from the vertical sidewall using a first wet etch chemistry, and removing the material from the excavated feature by etching it away using a second wet etch chemistry. The described method may be used to produce a MIM capacitor (800) suitable for an eDRAM device.

Abstract translation: 在挖掘特征（130,330,830）的垂直侧壁（132,332,832）上图案化金属（141,341,841）的方法包括将材料（350）放置在挖掘的特征中，使得部分 （435）暴露在材料上方的挖掘特征中，使用第一湿蚀刻化学法将金属的暴露部分从垂直侧壁上蚀刻出来，并且通过使用第二湿蚀刻化学法将其去除，从挖掘的特征中去除材料 湿蚀刻化学。 所描述的方法可以用于产生适合于eDRAM设备的MIM电容器（800）。