公开(公告)号：US20200260380A1

公开(公告)日：2020-08-13

申请号：US16783076

申请日：2020-02-05

Applicant: Intel Corporation

Inventor： Eric C. Samson ,  Murali Ramadoss ,  Marc Beuchat

IPC: H04W52/02 ,  G06F1/3234 ,  G06F1/324 ,  G06T1/20 ,  H04W52/18

Abstract: Methods and apparatus relating to advanced graphics Power State management are described. In one embodiment, measurement logic detects information about idle transitions and active transitions of a power-well of a processor. In turn, determination logic determines performance loss and/or energy gain based at least in part on the detected information and power-on latency of the power-well of the processor. Other embodiments are also disclosed and claimed.

公开(公告)号：US20200258191A1

公开(公告)日：2020-08-13

申请号：US16791514

申请日：2020-02-14

Applicant: Intel Corporation

Inventor： Adam T. Lake ,  Guei-Yuan Lueh ,  Balaji Vembu ,  Murali Ramadoss ,  Prasoonkumar Surti ,  Abhishek R. Appu ,  Altug Koker ,  Subramaniam M. Maiyuran ,  Eric C. Samson ,  David J. Cowperthwaite ,  Zhi Wang ,  Kun Tian ,  David Puffer ,  Brian T. Lewis

IPC: G06T1/60 ,  G06T1/20

Abstract: An apparatus to facilitate data prefetching is disclosed. The apparatus includes a memory, one or more execution units (EUs) to execute a plurality of processing threads and prefetch logic to prefetch pages of data from the memory to assist in the execution of the plurality of processing threads.

公开(公告)号：US10509576B2

公开(公告)日：2019-12-17

申请号：US15786424

申请日：2017-10-17

Applicant: Intel Corporation

Inventor： Inder M. Sodhi ,  Alon Naveh ,  Doron Rajwan ,  Ryan D. Wells ,  Eric C. Samson

IPC: G06F1/3206 ,  G06F3/06 ,  G06F1/3234 ,  G06F1/3287

Abstract: Embodiments of systems, apparatuses, and methods for energy efficiency and energy conservation including enabling autonomous hardware-based deep power down of devices are described. In one embodiment, a system includes a device, a static memory, and a power control unit coupled with the device and the static memory. The system further includes a deep power down logic of the power control unit to monitor a status of the device, and to transfer the device to a deep power down state when the device is idle. In the system, the device consumes less power when in the deep power down state than in the idle state.

公开(公告)号：US10460417B2

公开(公告)日：2019-10-29

申请号：US16010692

申请日：2018-06-18

Applicant: Intel Corporation

Inventor： Murali Ramadoss ,  Balaji Vembu ,  Eric C. Samson ,  Kun Tian ,  David J. Cowperthwaite ,  Altug Koker ,  Zhi Wang ,  Joydeep Ray ,  Subramaniam M. Maiyuran ,  Abhishek R. Appu

IPC: G06F9/48 ,  G06F9/38 ,  G06T1/20 ,  G06F9/50

Abstract: Embodiments described herein provide techniques enable a compute unit to continue processing operations when all dispatched threads are blocked. One embodiment provides for an apparatus comprising a thread dispatcher to dispatch a thread for execution; a compute unit having a single instruction, multiple thread architecture, the compute unit to execute multiple concurrent threads; and a memory coupled with the compute unit, the memory to store thread state for a suspended thread, wherein the compute unit is to: detect that all threads on the compute unit are blocked from execution, select a victim thread from the multiple concurrent threads, suspend the victim thread, store thread state of the victim thread to the memory, and replace the victim thread with an additional thread to be executed.

公开(公告)号：US10114441B2

公开(公告)日：2018-10-30

申请号：US15263274

申请日：2016-09-12

Applicant: INTEL CORPORATION

Inventor： Paul S. Diefenbaugh ,  Eugene Gorbatov ,  Andrew Henroid ,  Eric C. Samson ,  Barnes Cooper

IPC: G06F1/32 ,  G06F9/48

Abstract: In one embodiment an apparatus includes a multiplicity of processor components; one or more device components communicatively coupled to one or more processor components of the multiplicity of processor components; and a controller comprising logic at least a portion of which is in hardware, the logic to schedule one or more forced idle periods interspersed with one or more active periods, a forced idle period spanning a duration during which the multiplicity of processor components and the one or more device components are simultaneously placed in respective idle states that define a forced idle power state during isolated sub-periods of the forced idle period. Other embodiments are disclosed and claimed.

公开(公告)号：US20180285230A1

公开(公告)日：2018-10-04

申请号：US15477031

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Nikos Kaburlasos ,  Balaji Vembu ,  Josh B. Mastronarde ,  Altug Koker ,  Eric C. Samson ,  Abhishek R. Appu ,  Kiran C. Veernapu ,  Joydeep Ray ,  Vasanth Ranganathan ,  Sanjeev S. Jahagirdar

IPC: G06F11/30 ,  G06F1/32 ,  G05F1/10 ,  G05F1/571 ,  G06F11/32 ,  G06F11/34

CPC classification number: G06F11/3058 ,  G05F1/10 ,  G05F1/571 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  G06F11/322 ,  G06F11/328 ,  G06F11/3476

Abstract: Methods and apparatus relating to techniques for power management. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to generate a voltage/frequency curve for at least one of a core or a sub-core in a processor and manage an operating voltage level of the at least one of a core or a sub-core using the voltage/frequency curve. Other embodiments are also disclosed and claimed.

公开(公告)号：US09939879B2

公开(公告)日：2018-04-10

申请号：US14875930

申请日：2015-10-06

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Doron Rajwan ,  Jeremy J. Shrall ,  Eric C. Samson ,  Eliezer Weissmann ,  Ryan Wells

IPC: G06F13/14 ,  G06F1/32 ,  G06F1/30 ,  G06F1/26

CPC classification number: G06F1/324 ,  G06F1/26 ,  G06F1/30 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3243 ,  G06F13/14 ,  Y02D10/126

Abstract: In one embodiment, the present invention includes a method for determining that a non-core domain of a multi-domain processor is not operating at a frequency requested by the non-core domain, sending a request from the non-core domain to a power controller to reduce a frequency of a core domain of the multi-domain processor, and responsive to the request, reducing the core domain frequency. Other embodiments are described and claimed.

公开(公告)号：US09805438B2

公开(公告)日：2017-10-31

申请号：US14993421

申请日：2016-01-12

Applicant: Intel Corporation

Inventor： Nikos Kaburlasos ,  Eric C. Samson ,  Altug Koker

IPC: G06T1/20

CPC classification number: G06T1/20

Abstract: According to some embodiments, performance bottlenecks that arise in particular resources within a graphic processor unit may be alleviated by dynamically rebalancing workloads among the resources, with the goal of removing the current performance bottleneck, while at the same time maintaining power dissipation within a currently allocated power budget. In some embodiments this may be achieved by defining a separate clock domain for each of the plurality of graphics processor resources whose performance may then be rebalanced.

公开(公告)号：US09792064B2

公开(公告)日：2017-10-17

申请号：US15219183

申请日：2016-07-25

Applicant: Intel Corporation

Inventor： Inder M. Sodhi ,  Alon Naveh ,  Doron Rajwan ,  Ryan D. Wells ,  Eric C. Samson

IPC: G06F1/32 ,  G06F3/06

CPC classification number: G06F3/0625 ,  G06F1/3206 ,  G06F1/3278 ,  G06F1/3287 ,  G06F3/0634 ,  G06F3/0673 ,  Y02D10/157 ,  Y02D10/171

Abstract: Embodiments of systems, apparatuses, and methods for energy efficiency and energy conservation including enabling autonomous hardware-based deep power down of devices are described. In one embodiment, a system includes a device, a static memory, and a power control unit coupled with the device and the static memory. The system further includes a deep power down logic of the power control unit to monitor a status of the device, and to transfer the device to a deep power down state when the device is idle. In the system, the device consumes less power when in the deep power down state than in the idle state.

公开(公告)号：US09250910B2

公开(公告)日：2016-02-02

申请号：US14040472

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Linda L. Hurd ,  Wenyin Fu ,  Josh B. Mastronarde ,  Pradeep K. Golconda ,  Shalini Sankar ,  Eric C. Samson

IPC: G06F1/32 ,  G06F9/38

CPC classification number: G06F9/38 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/325 ,  Y02D10/126

Abstract: Methods and apparatus relating to a current change mitigation policy for limiting voltage droop in graphics logic are described. In an embodiment, logic inserts one or more bubbles in one or more Execution Unit (EU) logic pipelines or one or more sampler logic pipelines of a processor. The bubbles at least temporarily reduce execution of operations in one or more subsystems of the processor based at least partially on a comparison of a first value and one or more clamping threshold values. The first value is determined based at least partially on a summation of products of one or more event counts and dynamic capacitance weights for one or more subsystems of the processor. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了与用于限制图形逻辑中的电压下降的当前变化缓解策略有关的方法和装置。 在一个实施例中，逻辑在一个或多个执行单元（EU）逻辑管线或处理器的一个或多个采样器逻辑管线中插入一个或多个气泡。 至少部分地基于第一值和一个或多个钳位阈值的比较，气泡至少暂时地减少处理器的一个或多个子系统中的操作的执行。 至少部分地基于处理器的一个或多个子系统的一个或多个事件计数和动态电容权重的乘积的总和确定第一值。 还公开并要求保护其他实施例。