公开(公告)号：US10152401B2

公开(公告)日：2018-12-11

申请号：US14977659

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Ravi Rajwar ,  Bret L. Toll ,  Konrad K. Lai ,  Matthew C. Merten ,  Martin G. Dixon

IPC: G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F11/28 ,  G06F9/46 ,  G06F9/30 ,  G06F12/0811 ,  G06F9/38 ,  G11C7/10 ,  G06F11/22 ,  G06F11/263 ,  G06F12/0897 ,  G06F12/0817 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0875 ,  G06F11/14 ,  G06F11/25

Abstract: Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start a transactional region. Responsive to the first instruction, a checkpoint for a set of architecture state registers is generated and memory accesses from a processing element in the transactional region associated with the first instruction are tracked. A second instruction to detect transactional execution of the transactional region is then decoded. An operation is executed, responsive to decoding the second instruction, to determine if an execution context of the second instruction is within the transactional region. Then responsive to the second instruction, a first flag is updated. In some embodiments, a register may optionally be updated and/or a second flag may optionally be updated responsive to the second instruction.

公开(公告)号：US20180011748A1

公开(公告)日：2018-01-11

申请号：US15699823

申请日：2017-09-08

Applicant: Intel Corporation

Inventor： Haitham Akkary ,  Ravi Rajwar ,  Srikanth T. Srinivasan

IPC: G06F9/52 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F9/52 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3859

Abstract: A method and apparatus for post-retire transaction access tracking is herein described. Load and store buffers are capable of storing senior entries. In the load buffer a first access is scheduled based on a load buffer entry. Tracking information associated with the load is stored in a filter field in the load buffer entry. Upon retirement, the load buffer entry is marked as a senior load entry. A scheduler schedules a post-retire access to update transaction tracking information, if the filter field does not represent that the tracking information has already been updated during a pendency of the transaction. Before evicting a line in a cache, the load buffer is snooped to ensure no load accessed the line to be evicted.

公开(公告)号：US09665373B2

公开(公告)日：2017-05-30

申请号：US14752079

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Michael Lemay ,  David M. Durham ,  Barry E. Huntley ,  Vedvyas Shanbhogue ,  Ravi L. Sahita ,  Ravi Rajwar

IPC: G06F11/30 ,  G06F9/38 ,  G06F11/07

CPC classification number: G06F9/3802 ,  G06F9/3004 ,  G06F9/30076 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30189 ,  G06F9/46 ,  G06F11/0745 ,  G06F11/0751

Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for protecting confidential data with transactional processing in execute-only memory. The system may include a memory module configured to store an execute-only code page. The system may also include a transaction processor configured to enforce a transaction region associated with at least a portion of the code page. The system may further include a processor configured to execute a load instruction fetched from the code page, the load instruction configured to load at least a portion of the confidential data from an immediate operand of the load instruction if a transaction mode of the transaction region is enabled.

公开(公告)号：US09529645B2

公开(公告)日：2016-12-27

申请号：US14635790

申请日：2015-03-02

Applicant: Intel Corporation

Inventor： Suresh Srinivas ,  Stephen H. Dohrmann ,  Mingqiu Sun ,  Uma Srinivasan ,  Ravi Rajwar ,  Konrad K. Lai

IPC: G06F9/52 ,  G06F9/455 ,  G06F17/30 ,  G06F9/38 ,  G06F9/45

CPC classification number: G06F9/528 ,  G06F8/458 ,  G06F9/3842 ,  G06F9/45516 ,  G06F9/526 ,  G06F17/30168 ,  G06F17/30362 ,  Y10S707/99938

Abstract: Example methods and apparatus to manage object locks are disclosed. A disclosed example method includes intercepting a processor request to apply the lock on the object, identifying a performance history of the object based on a number of instances of contention, reducing computing resources of the processor by, when the number of instances is below a threshold value, generating a lock bypass for the object to cause speculative execution of target code within the object, and preventing speculative execution by applying the lock on the object when the number of instances is above the threshold value.

Abstract translation: 公开了用于管理对象锁的示例性方法和装置。 所公开的示例性方法包括拦截处理器请求以对对象施加锁定，基于竞争的多个实例来识别对象的性能历史，当实例数低于阈值时，减少处理器的计算资源 产生对象的锁旁路，以引起对象内的目标代码的推测执行，并且当实例数高于阈值时，通过对对象应用锁来防止推测执行。

公开(公告)号：US20160350221A1

公开(公告)日：2016-12-01

申请号：US15232551

申请日：2016-08-09

Applicant: Intel Corporation

Inventor： Omar M. Shaikh ,  Ravi Rajwar ,  Paul Caprioli ,  Muawya M. Al-Otoom

IPC: G06F12/0817 ,  G06F12/0875

CPC classification number: G06F9/3855 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/3016 ,  G06F9/3802 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/467 ,  G06F11/1448 ,  G06F11/1469 ,  G06F12/0828 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0875 ,  G06F2201/84 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/507 ,  G06F2212/6042 ,  G06F2212/62 ,  G06F2212/621 ,  G06F2213/0026

Abstract: Systems, apparatuses, and methods for improving TM throughput using a TM region indicator (or color) are described. Through the use of TM region indicators younger TM regions can have their instructions retired while waiting for older TM regions to commit.

Abstract translation: 描述了使用TM区域指示符（或颜色）来提高TM吞吐量的系统，装置和方法。 通过使用TM区域指标，年龄较小的TM区域可以在等待旧TM区域提交时，退出指令。

公开(公告)号：US20160202987A1

公开(公告)日：2016-07-14

申请号：US14757980

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Ravi Rajwar ,  Bret L. Toll ,  Konrad K. Lai ,  Matthew C. Marten ,  Martin G. Dixon

IPC: G06F9/38 ,  G06F9/30 ,  G06F12/08

CPC classification number: G06F11/28 ,  G06F9/30047 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/3802 ,  G06F9/3834 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/466 ,  G06F9/467 ,  G06F11/1407 ,  G06F11/2236 ,  G06F11/25 ,  G06F11/263 ,  G06F12/0811 ,  G06F12/0828 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/1032 ,  G06F2212/20 ,  G06F2212/283 ,  G06F2212/314 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/608 ,  G06F2212/621 ,  G11C7/1072

Abstract: Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start a transactional region. Responsive to the first instruction, a checkpoint for a set of architecture state registers is generated and memory accesses from a processing element in the transactional region associated with the first instruction are tracked. A second instruction to detect transactional execution of the transactional region is then decoded. An operation is executed, responsive to decoding the second instruction, to determine if an execution context of the second instruction is within the transactional region. Then responsive to the second instruction, a first flag is updated. In some embodiments, a register may optionally be updated and/or a second flag may optionally be updated responsive to the second instruction.