公开(公告)号：US20220100823A1

公开(公告)日：2022-03-31

申请号：US17442541

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Katalin Klara Bartfai-Walcott ,  Arkadiusz Berent ,  Vasuki Chilukuri ,  Mark Baldwin ,  Vasudevan Srinivasan ,  Naresh Sehgal ,  David Novick ,  Bartosz Gotowalski

IPC: G06F21/10 ,  H04L9/32 ,  G06Q30/04 ,  G06Q10/08

Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) for software defined silicon security are disclosed. Example apparatus include a trusted agent determiner to (i) determine respective reputation scores associated with a plurality of agents in a mesh network, the plurality of agents associated with a plurality of semiconductor devices, respective ones of the semiconductor devices including circuitry configurable to provide one or more features, and (ii) select, based on the respective reputation scores, a first agent from the plurality of the agents to transmit a request to activate or deactivate at least one of the one or more features. Example apparatus also include an agent interface to, in response to the request, broadcast an activation or deactivation of the least one of the one or more features to the mesh network to cause the trusted agent determiner to update the reputation score of the first agent.

公开(公告)号：US10761579B2

公开(公告)日：2020-09-01

申请号：US15668771

申请日：2017-08-04

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Vasudevan Srinivasan ,  Eugene Gorbatov ,  Andrew D. Henroid ,  Barnes Cooper ,  David W. Browning ,  Guy M. Therien ,  Neil W. Songer ,  Krishnakanth V. Sistla ,  James G. Hermerding, II

IPC: G06F1/32 ,  G06F1/26 ,  G06F1/324 ,  G06F1/20 ,  G06F1/3212 ,  G06F15/00

Abstract: In one embodiment, a system includes: a plurality of compute nodes to couple in a chassis; a first shared power supply to provide a baseline power level to the plurality of compute nodes; and an auxiliary power source to provide power to one or more of the plurality of compute nodes during operation at a higher power level than the baseline power level. Other embodiments are described and claimed.

公开(公告)号：US20190306654A1

公开(公告)日：2019-10-03

申请号：US16446823

申请日：2019-06-20

Applicant: INTEL CORPORATION

Inventor： Vasudevan Srinivasan ,  Barnes Cooper ,  Tawfik M Rahal-Arabi

IPC: H04W4/021 ,  H04W4/38

Abstract: Embodiments are generally directed to sharing of environmental data for client device usage. An embodiment of a client device includes a processor; an environmental sensor to sense an environmental condition, an output of the sensor being a local environmental sensor value; and a wireless receiver to receive environmental data for a certain proximity area from a second client device according to an environmental data sharing protocol via a wireless network. The environmental data sharing protocol allows receipt of the environmental data without requiring pairing, bonding, or other relationship of client devices.

公开(公告)号：US10397733B2

公开(公告)日：2019-08-27

申请号：US15283348

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Vasudevan Srinivasan ,  Barnes Cooper ,  Tawfik M Rahal-Arabi

IPC: H04W4/38 ,  H04W4/80 ,  H04W4/021 ,  H04L12/26 ,  H04W4/70

Abstract: Embodiments are generally directed to sharing of environmental data for client device usage. An embodiment of a client device includes a processor; an environmental sensor to sense an environmental condition, an output of the sensor being a local environmental sensor value; and a wireless receiver to receive environmental data for a certain proximity area from a second client device according to an environmental data sharing protocol via a wireless network. The environmental data sharing protocol allows receipt of the environmental data without requiring pairing, bonding, or other relationship of client devices.

公开(公告)号：US20180373287A1

公开(公告)日：2018-12-27

申请号：US15632000

申请日：2017-06-23

Applicant: Intel Corporation

Inventor： Asma H. Al-Rawi ,  Federico Ardanaz ,  Jonathan M. Eastep ,  Dorit Shapira ,  Krishnakanth Sistla ,  Nikhil Gupta ,  Vasudevan Srinivasan ,  Chris MacNamara

IPC: G06F1/06 ,  G06F1/04 ,  G06F1/08 ,  G06F9/50

Abstract: An apparatus system is provided which comprises: a first component and a second component; a first circuitry to assign the first component to a first group of components, and to assign the second component to a second group of components; and a second circuitry to assign a first maximum frequency limit to the first group of components, and to assign a second maximum frequency limit to the second group of components, wherein the first component and the second component are to respectively operate in accordance with the first maximum frequency limit and the second maximum frequency limit.

公开(公告)号：US20180365022A1

公开(公告)日：2018-12-20

申请号：US15625423

申请日：2017-06-16

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Nikhil Gupta ,  Krishnakanth V. Sistla ,  Corey D. Gough ,  Vasudevan Srinivasan ,  Eliezer Weissmann ,  Stephen H. Gunther ,  Eugene Gorbatov ,  Russell J. Fenger ,  Guy M. Therien

IPC: G06F9/44 ,  G06F3/06

Abstract: Embodiments of processors, methods, and systems for dynamic offlining and onlining of processor cores are described. In an embodiment, a processor includes a plurality of cores, a core status storage location, and a core tracker. Core status information for at least one of the plurality of cores is the be stored in the core status storage location. The core status information is to include a core state to be used by a software scheduler. The core state is to be one of a plurality of core state values including an online value, a requesting-to-go-offline value, and an offline value. The core tracker is to track usage of the at least one core and to change the core state from the online value to the requesting-to-go-offline value in response to determining that usage has reached a predetermined threshold.

公开(公告)号：US12066853B2

公开(公告)日：2024-08-20

申请号：US18329492

申请日：2023-06-05

Applicant: Intel Corporation

Inventor： Vasudevan Srinivasan ,  Krishnakanth V. Sistla ,  Corey D. Gough ,  Ian M. Steiner ,  Nikhil Gupta ,  Vivek Garg ,  Ankush Varma ,  Sujal A. Vora ,  David P. Lerner ,  Joseph M. Sullivan ,  Nagasubramanian Gurumoorthy ,  William J. Bowhill ,  Venkatesh Ramamurthy ,  Chris MacNamara ,  John J. Browne ,  Ripan Das

IPC: G06F1/08 ,  G06F1/3203 ,  G06F1/324 ,  G06F9/30 ,  G06F9/455

CPC classification number: G06F1/08 ,  G06F1/3203 ,  G06F1/324 ,  G06F9/30101 ,  G06F9/45558 ,  G06F2009/45591 ,  Y02D10/00

Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.

公开(公告)号：US20240095315A1

公开(公告)日：2024-03-21

申请号：US18474081

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Katalin Bartfai-Walcott ,  Mariusz Oriol ,  Vasudevan Srinivasan ,  Peggy Irelan ,  Mariusz Stepka ,  Kaitlin Murphy ,  Bharat Pillilli ,  Mark Baldwin ,  Mateusz Bronk ,  Fariaz Karim ,  Arkadiusz Berent ,  Vasuki Chilukuri

IPC: G06F21/10 ,  G06F9/455

CPC classification number: G06F21/107 ,  G06F9/45558 ,  G06F2009/4557

Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement license management solutions for software defined silicon (SDSi) products are disclosed. Example license management solutions disclosed herein include, but are not limited to, virtual resource migration using SDSi, resource configuration management using SDSi, hardware self-configuration using SDSi, reduced footprint agents using SDSi, performing SDSi usage evaluation and corresponding license transfer responsive to detected and/or predicted failures, transferring node locked SDSi licenses, transfer of SDSi licenses without a trusted license server, community license generation, expirable SDSi licenses via a reliable clock, non-node locked licenses via blockchain, and activating hardware features with a pre-generated hardware license.

公开(公告)号：US20230315143A1

公开(公告)日：2023-10-05

申请号：US18329492

申请日：2023-06-05

Applicant: Intel Corporation

Inventor： Vasudevan Srinivasan ,  Krishnakanth V. Sistla ,  Corey D. Gough ,  Ian M. Steiner ,  Nikhil Gupta ,  Vivek Garg ,  Ankush Varma ,  Sujal A. Vora ,  David P. Lerner ,  Joseph M. Sullivan ,  Nagasubramanian Gurumoorthy ,  William J. Bowhill ,  Venkatesh Ramamurthy ,  Chris MacNamara ,  John J. Browne ,  Ripan Das

IPC: G06F1/08 ,  G06F1/3203 ,  G06F9/30 ,  G06F9/455 ,  G06F1/324

CPC classification number: G06F1/08 ,  G06F1/3203 ,  G06F9/30101 ,  G06F9/45558 ,  G06F1/324 ,  G06F2009/45591

Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.

公开(公告)号：US11650851B2

公开(公告)日：2023-05-16

申请号：US16678888

申请日：2019-11-08

Applicant: Intel Corporation

Inventor： Stephen T. Palermo ,  Nikhil Gupta ,  Vasudevan Srinivasan ,  Christopher MacNamara ,  Sarita Maini ,  Abhishek Khade ,  Edwin Verplanke ,  Lokpraveen Mosur

IPC: G06F9/50 ,  G06F9/455

CPC classification number: G06F9/505 ,  G06F9/45558 ,  G06F9/5044 ,  G06F2009/4557 ,  G06F2009/45595

Abstract: Methods, apparatus, systems and machine-readable storage media of an edge computing device using an edge server CPU with dynamic deterministic scaling is disclosed. A processing circuitry arrangement includes processing circuitry with processor cores operating at a center base frequency and memory. The memory includes instructions configuring the processing circuitry to configure a first set of the processor cores of the CPU to switch the operating at the center base frequency to operating at a first modified base frequency, and a second set of the processor cores to switch the operating at the center base frequency to operating at a second modified base frequency. A same processor core within the first set or the second set can be configured to switch operating between the first modified base frequency or the second modified base frequency.