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    Instruction and logic to provide a secure cipher hash round functionality
    32.
    发明授权
    Instruction and logic to provide a secure cipher hash round functionality 有权

    公开(公告)号：US10038550B2

    公开(公告)日：2018-07-31

    申请号：US13962933

    申请日：2013-08-08

    Applicant: Intel Corporation

    Inventor： Vinodh Gopal ,  Wajdi K. Feghali

    IPC: H04L9/06

    CPC classification number: H04L9/0643 ,  G06F9/30007 ,  G06F9/30036 ,  H04L9/0625

    Abstract: Instructions and logic provide secure cipher hashing algorithm round functionality. Some embodiments include a processor comprising: a decode stage to decode an instruction for a secure cipher hashing algorithm, the first instruction specifying a source data, and one or more key operands. Processor execution units, are responsive to the decoded instruction, to perform one or more secure cipher hashing algorithm round iterations upon the source data, using the one or more key operands, and store a result of the instruction in a destination register. One embodiment of the instruction specifies a secure cipher hashing algorithm round iteration using a Feistel cipher algorithm such as DES or TDES. In one embodiment a result of the instruction may be used in generating a resource assignment from a request for load balancing requests across the set of processing resources.

    Techniques for parallel data compression
    34.
    发明授权
    Techniques for parallel data compression 有权

    公开(公告)号：US09853660B1

    公开(公告)日：2017-12-26

    申请号：US15468061

    申请日：2017-03-23

    Applicant: INTEL CORPORATION

    Inventor： Vinodh Gopal ,  Kirk S. Yap ,  Daniel F. Cutter ,  James D. Guilford ,  Wajdi K. Feghali

    IPC: H03M7/00 ,  H03M7/34 ,  H03M7/30 ,  H03M7/40

    CPC classification number: H03M7/3086 ,  H03M7/40 ,  H03M7/6023

    Abstract: Techniques and apparatus for parallel data compression are described. An apparatus to provide parallel data compression may include at least one memory and logic for a compression component, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to provide at least one data input sequence to a plurality of compression components, determine compression information for the plurality of compression components, and perform a compression process on the at least one data input sequence via the plurality of compression components to generate at least one data output sequence, the plurality of compression components to perform the compression process in parallel based on the compression information.

    Apparatus and method of execution unit for calculating multiple rounds of a skein hashing algorithm
    37.
    发明授权
    Apparatus and method of execution unit for calculating multiple rounds of a skein hashing algorithm 有权
    用于计算多轮skein散列算法的执行单元的装置和方法

    公开(公告)号：US09569210B2

    公开(公告)日：2017-02-14

    申请号：US15203610

    申请日：2016-07-06

    Applicant: Intel Corporation

    Inventor： Gilbert M. Wolrich ,  Kirk S. Yap ,  James D. Guilford ,  Erdinc Ozturk ,  Vinodh Gopal ,  Wajdi K. Feghali ,  Sean M. Gulley ,  Martin G. Dixon

    IPC: G06F9/30 ,  G06F9/38 ,  H04L9/06

    CPC classification number: G06F9/30029 ,  G06F9/30007 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/3885 ,  G06F9/3895 ,  H04L9/0643

    Abstract: An apparatus is described that includes an execution unit within an instruction pipeline. The execution unit has multiple stages of a circuit that includes a) and b) as follows: a) a first logic circuitry section having multiple mix logic sections each having: i) a first input to receive a first quad word and a second input to receive a second quad word; ii) an adder having a pair of inputs that are respectively coupled to the first and second inputs; iii) a rotator having a respective input coupled to the second input; iv) an XOR gate having a first input coupled to an output of the adder and a second input coupled to an output of the rotator. b) permute logic circuitry having inputs coupled to the respective adder and XOR gate outputs of the multiple mix logic sections.

    Abstract translation: 描述了包括指令流水线内的执行单元的装置。 执行单元具有包括a）和b）的电路的多个级，如下：a）具有多个混合逻辑部分的第一逻辑电路部分，每个混合逻辑部分具有：i）用于接收第一四字和第二输入的第一输入 接收第二个四字; ii）具有分别耦合到所述第一和第二输入的一对输入的加法器; iii）具有耦合到第二输入的相应输入的旋转器; iv）具有耦合到加法器的输出的第一输入和耦合到转子的输出的第二输入的异或门。 b）置换逻辑电路，其具有耦合到多个混合逻辑部分的相应加法器和异或门输出的输入。

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