公开(公告)号：US10250272B2

公开(公告)日：2019-04-02

申请号：US15681857

申请日：2017-08-21

Applicant: MaxLinear, Inc.

Inventor： Jianyu Zhu

IPC: H03M1/06 ,  H03M1/08 ,  H03M1/74 ,  H03M1/66

Abstract: A digital-to-analog converter (DAC) may have an encoder that generates a multi-bit output based on a multi-bit input, a plurality of first converter elements, with each first converter element generating an output according to a single bit of the multi-bit output of the encoder; and a combiner that generates a combined output based on combining outputs from the plurality of first converter elements. The number of bits in the multi-bit input being two or more and the number of bits in the multi-bit output being greater than the number of bits in the multi-bit input. The DAC may also have one or more second converter elements, with second converter element generating an output according to a single bit, and the combiner may generates the combined output based on combining outputs from the plurality of first converter elements with outputs from the one or more second converter elements.

公开(公告)号：US10158368B2

公开(公告)日：2018-12-18

申请号：US15997336

申请日：2018-06-04

Applicant: MaxLinear, Inc.

Inventor： Gaurav Chandra ,  Tao Zeng ,  Shantha Murthy Prem Swaroop ,  Jianyu Zhu

IPC: H03M1/06 ,  H03M1/66

Abstract: A digital-to-analog converter (DAC) controller system may be configured for controlling switching in an associated digital-to-analog converter (DAC), based on a plurality of system inputs that include at least a first system input corresponding to an input applied to the DAC for controlling switching therein, and a second system input that includes a reference control signal. The DAC controller system may include a logic gate circuit that generates a gate output based on two gate inputs that include the first system input and an input set based on the second system input; and a plurality of timing circuits that generate timing outputs for controlling timing of switching in the DAC, which include at least one timing circuit that generates a timing output based on the gate output, with the timing output configured for application in conjunction with and for adjusting a timing output of another timing circuit.

公开(公告)号：US20180287624A1

公开(公告)日：2018-10-04

申请号：US15997336

申请日：2018-06-04

Applicant: MaxLinear, Inc.

Inventor： Gaurav Chandra ,  Tao Zeng ,  Shantha Murthy Prem Swaroop ,  Jianyu Zhu

IPC: H03M1/06 ,  H03M1/66

CPC classification number: H03M1/0624 ,  H03M1/66

Abstract: A digital-to-analog converter (DAC) controller system may be configured for controlling switching in an associated digital-to-analog converter (DAC), based on a plurality of system inputs that include at least a first system input corresponding to an input applied to the DAC for controlling switching therein, and a second system input that includes a reference control signal. The DAC controller system may include a logic gate circuit that generates a gate output based on two gate inputs that include the first system input and an input set based on the second system input; and a plurality of timing circuits that generate timing outputs for controlling timing of switching in the DAC, which include at least one timing circuit that generates a timing output based on the gate output, with the timing output configured for application in conjunction with and for adjusting a timing output of another timing circuit.

公开(公告)号：US09985777B2

公开(公告)日：2018-05-29

申请号：US15419063

申请日：2017-01-30

Applicant: MaxLinear, Inc.

Inventor： Jianyu Zhu ,  Sheng-Yu Peng ,  Rodney Chandler ,  Pawan Tiwari ,  Rahul Bhatia ,  Eric Fogleman

IPC: H04L7/033 ,  H04B1/10 ,  H03M1/12

CPC classification number: H04L7/0334 ,  H03M1/1215 ,  H03M1/1245

Abstract: A radio frequency (RF) receiver may comprise a first sampling module that is operable to sample in a first level at a particular main sampling rate; a plurality of second-level sampling modules, wherein each of the plurality of second-level sampling modules is operable to sample in a second level, an output of the first level, at a second sampling rate that is reduced compared to the main sampling rate; and a plurality of third-level modules, each comprising a plurality of third-stage sampling sub-modules that are operable to sample at a third sampling rate that is reduced compared to the second sampling rate, and a plurality of corresponding analog-to-digital conversion (ADC) sub-modules.

公开(公告)号：US09698806B2

公开(公告)日：2017-07-04

申请号：US15218586

申请日：2016-07-25

Applicant: MaxLinear, Inc.

Inventor： Jianyu Zhu

IPC: H03M1/66 ,  H03M1/08 ,  H03M1/00 ,  H04B15/02 ,  H03M1/74

CPC classification number: H03M1/0863 ,  H03M1/002 ,  H03M1/66 ,  H03M1/664 ,  H03M1/742 ,  H04B15/02

Abstract: Methods and systems are provided for dynamic power switching in current-steering digital-to-analog converters (DACs). A DAC circuit may be configured to apply digital-to-analog conversions based on current steering, and to particularly incorporate use of dynamic power switching during conversions. The DAC circuit may comprise a main section, which may connect a main supply voltage to a main current source. The main section may comprise a positive-side branch and a negative-side branch, which may be configured to steer positive-side and negative-side currents, such as in a differential manner, to effectuate the conversions. The dynamic power switching may be applied, for example, via a secondary section connecting a main current source in the DAC circuit to a secondary supply voltage. The secondary supply voltage may be configured such that it may be less than the main supply voltage used in driving the current steering in the DAC circuit.

公开(公告)号：US09559835B2

公开(公告)日：2017-01-31

申请号：US14563476

申请日：2014-12-08

Applicant: MaxLinear, Inc.

Inventor： Jianyu Zhu ,  Sheng-Yu Peng ,  Rodney Chandler ,  Pawan Tiwari ,  Rahul Bhatia ,  Eric Fogleman

IPC: H04B1/10 ,  H04L7/033 ,  H03M1/12

CPC classification number: H04L7/0334 ,  H03M1/1215 ,  H03M1/1245

Abstract: A signal receiver may comprise circuitry for applying multi-level sampling to an input signal, using a plurality of sampling rates that comprises at least two different sampling rates, and circuitry for processing one or more outputs of the multi-level sampling. The processing may comprises sampling at a sampling rate that is different than each of the plurality of sampling rates used during the multi-level sampling and applying analog-to-digital conversion. At least one of the sampling rates used during the multi-level sampling and/or the sampling rate used during the processing may be set based on configuring of one or more clock signals used during the multi-level sampling and/or during the processing. At least one of the one or more clock signals may be configured based on reduction of frequency of a corresponding base clock signal.

Abstract translation: 信号接收机可以包括用于使用包括至少两个不同采样速率的多个采样速率以及用于处理多电平采样的一个或多个输出的电路将多电平采样应用于输入信号的电路。 处理可以包括以与在多级采样期间使用的多个采样率中的每一个不同的采样率进行采样并且应用模数转换。 在处理期间使用的多级采样和/或采样率期间使用的采样率中的至少一个可以基于在多级采样期间和/或处理期间使用的一个或多个时钟信号的配置来设置。 可以基于对应的基本时钟信号的频率的降低来配置一个或多个时钟信号中的至少一个。

公开(公告)号：US20170019118A1

公开(公告)日：2017-01-19

申请号：US15213731

申请日：2016-07-19

Applicant: MaxLinear, Inc.

Inventor： Jianyu Zhu

IPC: H03M1/08 ,  H03M1/66

CPC classification number: H03M1/08 ,  H03M1/0617 ,  H03M1/066 ,  H03M1/66 ,  H03M1/74

Abstract: Methods and systems are provided for enhanced digital-to-analog conversions. A segmentation-based digital-to-analog converter (DAC) may be configured for applying digital-to-analog conversions to N-bit inputs. The segmentation-based DAC may comprise a plurality of DAC elements, with each DAC element being operable to apply digital-to-analog conversion based on a single bit, and an encoder operable to generate an x-bit output. The number of DAC elements may be different than number of bits (N) in inputs to the DAC. One or more bits of the N-bit input may be applied to the encoder to generate the x-bit output, with each bit in the x-bit output being applied to a corresponding one of the plurality of DAC elements. Remaining one or more bits of the N-bit input, if any, may be applied directly to a corresponding one or more of the plurality of DAC elements.

Abstract translation: 提供了用于增强数模转换的方法和系统。 可以配置基于分段的数模转换器（DAC）以将数模转换应用于N位输入。 基于分段的DAC可以包括多个DAC元件，其中每个DAC元件可操作以基于单个位来施加数字模拟转换，以及编码器，其可操作以产生x位输出。 DAC元件的数量可能不同于输入到DAC的位数（N）。 N位输入的一个或多个位可以被施加到编码器以产生x位输出，x位输出中的每个位被施加到多个DAC元件中的对应的一个。 将N位输入的一个或多个位（如果有的话）剩余可以直接施加到多个DAC元件中对应的一个或多个。